Context

Discovered while measuring FE-board VREF (REF3425, 2.500 V ±0.05 %) through the Sparrow Test Adapter R0 to an external Siglent SDM3055 DMM via Phoenix terminals P3 (DMM+) / P4 (DMM−). See linked test case PT-PWR.10 (id 270, project 1) and the resolved question E-007 (id 54) on this project for the diagnostic chain.

Problem

TA R0 has no dedicated low-impedance ground return between the DUT board AGND and the Phoenix terminal block's DMM− pin. The J4–J9 IDC ground pins on TA R0 are deliberately routed to the host MPIO ADC as signals, so they cannot carry return current. As a consequence, the TA's local 0 V rail sits at a +5 to +15 mV bias relative to the DUT's AGND, depending on incidental cable / chassis paths. Any precision DMM measurement via the TA Phoenix terminals inherits this bias.

Practical effect: PT-PWR.10 cannot be a precision check of REF3425; only PT-PWR.06 (N-Top-internal ADC chain) verifies the 2.500 V ±0.05 % spec.

Decision

Each J-connector that exposes a DUT GND pin shall provide a populatable jumper that bonds that GND pin to TA's measurement ground. The jumper preserves the existing "GND pin as host-measurable signal" capability when unpopulated, and enables precision DMM measurement when populated. The two modes are mutually exclusive by design.

Per-connector jumper

• J5 — required minimum. Bonds J5 GND to TA AGND when populated, providing the low-impedance return for the FE VREF precision measurement (PT-PWR.10) and any future precision DMM tests routed via J5.
• J4, J6, J7, J8, J9 — strongly recommended to apply the same pattern, so any J-connector can be the precision-measurement source without ad-hoc workarounds. Defer per-connector inclusion to TA R1 layout review based on which connectors host precision-measurement targets in the current verification plan; bias toward "include all" to avoid an R2 revisit.

Operator contract

• Before any DMM-based precision measurement: populate the jumper on the J-connector being measured.
• After the precision measurement: remove the jumper, so the GND-continuity check on host MPIO still verifies the DUT-side GND propagation through the IDC connector (which is what that test is for — a populated jumper would just measure TA's local GND, not the DUT path).

Jumper-state sensing (recommended)

Add an MPIO sense net per jumper (high-impedance pull-up on TA, low on the jumper-down side) that reads HIGH when the jumper is populated. The Maestro test framework can then:

• Refuse to start a precision DMM measurement if the relevant jumper is not populated → turns a silent ground-bias error into a hard fail with a clear operator-facing message.
• Refuse to start a GND-continuity check if any jumper is populated → prevents an operator from accidentally "passing" the continuity check via the jumper rather than the DUT path.

Test sequencing

Production flow should not require operator intervention mid-run. Two acceptable patterns:

1. GND-continuity tests run first (jumpers unpopulated). Pause with operator prompt. Jumpers populated. Precision DMM tests run. Pause. Jumpers removed. Remaining tests run.
2. Precision DMM tests are diagnostic-only (not part of standard production), invoked manually as a calibration / acceptance step. Standard production keeps jumpers unpopulated; precision tests are operator-driven sessions with the jumper present.

The PT-PWR.10 routing smoke test (current widened window 2.490–2.510 V) remains valid in either mode.

Phoenix DMM− still required

The Phoenix terminal block's DMM− pin must reach TA AGND via 0-Ω strap, chassis bond, or dedicated header — see the original two options below. The per-connector jumpers complete the DUT→TA path; the Phoenix DMM− completes the TA→DMM path. Both halves are necessary.

Acceptable Phoenix-side implementations (carried over from the original draft):

1. A dedicated GND pin (e.g. PHX_GND / DMM_GND) on the Phoenix terminal block, wired directly to the TA's GND plane via a 0-Ω strap and brought out as a single hard-wired return.
2. The Phoenix terminal block's mounting screws / chassis tied to the TA GND plane, allowing the DMM− cable to bond via a short stub.

Cable reach

The Phoenix DMM− must be reachable by a short cable (≤ 30 cm) so it can be used by all external DMM measurements (precision + general-purpose).

Why this matters

Without this, any precision DMM-based measurement via the TA is limited to roughly ±15 mV resolution after bias subtraction, which is insufficient for verifying:

• VREF precision references (REF3425 / REF3425A spec ±1.25 / ±2.5 mV)
• Power-rail accuracy claims tighter than ±10 mV
• High-resolution ADC linearity tests routed via TA to an external DMM

Workaround for TA R0

An ad-hoc wire from SDM3055 ground to FE-board AGND reduces the bias from ~10 mV to ~3 mV (probe check #1 in E-007). Acceptable for the current PT-PWR.10 routing smoke test (window widened to ±0.4 %), but not a substitute for the TA R1 fix.

Related artifacts

• Question entry: E-007 on this project (id 54) — diagnostic chain + resolution.
• Schematic-bug entry: E-006 on this project (id 53) — also fix in TA R1.
• Test case: PT-PWR.10 (id 270) on project 1.
• Maestro implementation: tests/fe_J5_vref.yaml in ESH10000633_SparrowUnitTest_v01.

Context

The audio loopback test PT-SIG.04 (MIC_BIAS / Audio Load) uses a DSUB-9 loopback plug fitted with 680 Ω pull-ups to 2.5 V on each MIC_IN line. The 680 Ω + the FE board's switched 2.2 kΩ load form a voltage divider whose mid-point at MIC_IN reports ≈ 1.910 V when the FE-side load is asserted; the YAML window 1.86 V ≤ V_MIC ≤ 1.95 V corresponds to R_bias varying ±2.5 % around 2.2 kΩ (matches SIG-08 acceptance RLOAD_BIAS 2156–2264 Ω).

On Sparrow Test Adapter R0, the 2.5 V supply for the loopback plug must come from somewhere external — typically an ad-hoc bench supply or a hand-wired tap off a nearby reference. There is no defined TA → loopback-plug power path.

Decision

TA R1 shall provide a dedicated 2.5 V + GND output connector, intended to feed the DSUB-9 audio loopback plug.

Acceptable implementations:

1. A 2-pin header (e.g. 2.54 mm pitch) labelled DSUB_VREF_OUT / GND, wired to a buffered 2.5 V source on TA.
2. A small Phoenix-style screw-terminal pair, similarly labelled.

The connector shall sit physically near the J6 / DSUB-9 routing area so a short jumper cable can reach the DSUB loopback plug without crossing the precision-measurement paths.

Source for the 2.5 V

Two acceptable sources on TA R1:

1. Dedicated buffered reference on TA — e.g. a REF3425 (±0.05 %) followed by a unity-gain op-amp buffer with adequate output drive. Cleanest electrical option; isolates the loopback load from any other precision-reference user on TA and decouples this output from the boards-under-test.
2. Tap of an existing TA reference, brought out via dedicated wiring (not via any J-connector IDC path which is under test).

Option 1 is preferred — keeps the TA self-sufficient for this measurement chain and avoids cross-coupling fixture state to the boards-under-test.

Output drive budget

Worst-case sink for the loopback plug: 4 MIC_IN lines, each pulling ≈ 0.87 mA through their 680 Ω pull-up when the FE-side R_bias load is engaged → total ≤ ~3.5 mA simultaneous. Pick a 2.5 V source rated ≥ 10 mA with low output impedance (≤ 1 Ω) to ensure < 5 mV droop under load, which keeps the loopback divider within the existing ±2.5 % window.

Why this matters

• Eliminates the ad-hoc external-supply dependency for PT-SIG.04 on the bench.
• Makes the test self-contained: a tester running PT-SIG.04 needs only the TA + the DSUB loopback plug, no external 2.5 V supply.
• Improves repeatability: a TA-sourced 2.5 V is one well-characterised quantity per fixture; "whatever bench supply happened to be at hand" is not.
• Removes a possible silent-failure mode (operator forgot to attach the bench supply, loopback reads 0 V, test still appears to run but bias measurement is meaningless).

Considerations / open

• Labelling on TA silkscreen must make the polarity and voltage unambiguous so an operator cannot accidentally short the loopback's 5 V mic-supply line into the 2.5 V output.
• Should there be a sense / monitor net that reads back the 2.5 V output via a host MPIO ADC channel? If yes, the Maestro test framework can refuse to start PT-SIG.04 if the output is missing or out of spec. Worth ~1 MPIO channel; recommended.
• DSUB loopback plug revision: this decision implies a matched revision of the loopback plug accessory that uses the TA-provided 2.5 V rather than an external supply. Track separately or note in the loopback plug BOM.

Related artifacts

• Test case: PT-SIG.04 (id 28) on project 1 — Audio Load / MIC_BIAS test, currently status=pass in PLEASE with the ad-hoc external 2.5 V supply.
• Requirement: SIG-08 (Audio Load) — describes the MIC_BIAS sourcing spec the loopback test verifies.
• Maestro implementation: tests/fe_J6_audio.yaml in ESH10000633_SparrowUnitTest_v01.
• Companion TA R1 decisions: E-008 (per-J-connector DMM_GND jumpers), E-006 (schematic mfg P/N fix on EGP10001847).

Decision

For Sparrow Test Adapter R1, route a dedicated low-impedance ground return from the DUT (FE-board AGND) to Phoenix terminal P4 (DMM−). This return must not share path with the J4–J9 IDC GND pins (which are deliberately routed to host MPIO ADC channels as measurable signals on R0 and so cannot carry the DMM-return current).

Why

Confirmed via empirical probing 2026-05-27 (calibrated SDM3055 at 192.168.0.6):

The ad-hoc wire test cuts the bias from +10 mV to +3 mV — direct confirmation that the dominant error source is a shared-ground impedance bias, not the relay matrix or the SDM3055 calibration. A dedicated AGND return clears the bulk of the offset; the residual ~3 mV is plausibly fixture-cable / chassis loop pickup, addressable later if needed.

Path forward

1. Add DMM_GND net on TA R1 schematic — dedicated trace from a clean AGND star point on the test-adapter side back to Phoenix P4.
2. Verify routing has no shared current path with any signal return (especially the J4–J9 IDC GND-monitored pins).
3. Re-measure PT-PWR.10 on the prototyped R1 and confirm the readback at TA matches C46 within REF3425 ±0.05 % (±1.25 mV).
4. Tighten tests/fe_J5_vref.yaml window back from ±10 mV → ±2 mV once the R1 fix is verified.

Resolves

PLEASE entry E-007 on project 14 (root cause investigation). PT-PWR.10 window stays widened to ±10 mV (tests/fe_J5_vref.yaml v1.0.235) until R1 lands.

Maestro test artifacts referenced

• tests/fe_J5_vref.yaml — measurement-window docstring documents the bias and references this entry.
• Linked PLEASE testcase: PT-PWR.10 (id 270) in project 1.

Applied 2026-05-15 to DUT-01 (S/N P0). Not present in ESH10000654 R0 schematic.

What

Tied four J7 nets together onto a single rail (Rail A):

• FE_MPIO_8
• FE_MPIO_10
• RELAY1
• RELAY3

Plus added a 10 kΩ 5 % pull-up to 2.5 V on the rail.

Why

Prototype implementation of next-revision relay-driver readback. The carry-forward originates in ESH10000540/R3/02_Implementation/DesignFiles/DesignLog_Sparrow fixture_electronics.xlsx 2026-05-12.

Coarse-grained limitation

This 2-rail ganged version cannot distinguish which odd-indexed relay fired:

• RELAY1 closed → Rail A goes low (but so does it for RELAY3)
• RELAY3 closed → Rail A goes low (indistinguishable from RELAY1)

Same coarseness for FE_MPIO_8 vs FE_MPIO_10.

Original design intent was 4-channel per-relay readback; that's deferred to next rev (see notice "Next-rev relay-pin fix decision").

Test impact

This patch IS the topology that fe_J7_mpio_relay.yaml Step 2 ("FE_MPIO + RELAY fabric") depends on. Without the patch, the fabric step would produce floating readings.

Components added by patch

• Pull-up resistor: 10 kΩ ±5 % (not in BOM — added physically; suggest tracking as EGP10000097 for any future order if 1 % is acceptable)
• Wire-wraps / jumper wires tying the four J7 pins to the rail node

Applied 2026-05-15 to DUT-01 (S/N P0). Not present in ESH10000654 R0 schematic.

What

Tied four J7 nets together onto a single rail (Rail B):

• FE_MPIO_9
• FE_MPIO_11
• RELAY2
• RELAY4

Plus added a 10 kΩ 5 % pull-up to 2.5 V on the rail.

Why

Same as patch #1 — prototype next-revision relay-driver readback. Even-indexed pair this time.

Coarse-grained limitation

Cannot distinguish:

• RELAY2 vs RELAY4 firing on Rail B
• FE_MPIO_9 vs FE_MPIO_11 driving

Test impact

Co-required with patch #1 for fe_J7_mpio_relay.yaml Step 2. Without the patch, FE_MPIO_9/11 and RELAY2/4 readings would float on the test fixture.

Components added by patch

• Pull-up resistor: 10 kΩ ±5 % (same note as patch #1 re BOM tracking)
• Wire-wraps / jumper wires

Applied 2026-05-15 to DUT-01 (S/N P0).

What

R48 was missing on the as-assembled board — present in schematic, not fitted at assembly. Patched in 2026-05-15.

Schematic value

0 Ω jumper (per Sparrow_TA_R0.pdf — schematic shows R48 as a 0 Ω link in the relay-driver area near U2 TBD62083 / U1 74HCS86).

Why patched

R0 assembly/BOM defect — restore intended schematic functionality. Original schematic was correct; assembler did not mount R48 (likely a placement-list omission, not a deliberate DNP). Patch returns the board to the as-designed state.

⚠️ Open — function TBD

The specific net function of R48 has not been confirmed. From the schematic R48 is a 0 Ω in the relay-driver enable / output area, but the exact role (which signal it links) needs a careful trace of the schematic and netlist. Tracked as Q-TA-01 (separate question entity).

Severity = warning until Q-TA-01 is answered: if R48 turns out to be critical for one of the test-rig functions (e.g. enabling a relay-driver output stage that the production-test depends on), then only patched units can be used. If R48 is purely a debug / test-point link, lesser impact.

Action items

1. Trace R48 from schematic + NetList_Sparrow_TA_R0.qcv (when netlist export is added to project 14's DesignFiles) to confirm net role.
2. Update next-rev BOM to ensure R48 is mounted by the assembler (no longer DNP).
3. If a future production order of ESH10000654 R0 is placed without this patch, flag for rework before the board is used as a test adapter.

Context

The current TA patches #1 + #2 (DUT-01 / S/N P0, 2026-05-15) implement a 2-rail ganged relay-driver readback:

• Rail A = FE_MPIO_8, FE_MPIO_10, RELAY1, RELAY3 + 10K pull-up to 2.5 V
• Rail B = FE_MPIO_9, FE_MPIO_11, RELAY2, RELAY4 + 10K pull-up to 2.5 V

This is coarser than the original 4-channel intent — cannot distinguish RELAY1 vs RELAY3 on Rail A, nor RELAY2 vs RELAY4 on Rail B.

What needs to be decided for next TA revision

How to provide per-relay readback so that any single relay firing can be unambiguously identified by the host-side MPIO reading.

Candidate approaches (sketch — pick one for the next-rev design review):

1. 4 separate rails, each with one MPIO + one RELAY + dedicated pull-up. Cleanest; uses 8 host-MPIO channels (4 sense + 4 unchanged), but only 4 effective.
2. Voltage-divider encoding — each relay drops the rail to a different voltage (e.g. via different in-line series resistors). Uses fewer host MPIOs but is fragile to drift.
3. Time-multiplexed enable — only fire one relay at a time during the test step, so even the ganged rail unambiguously identifies which one. Software-only fix, no TA change.

Option 3 is the lowest-effort fix and probably right for production test. Worth confirming before spending a TA revision on hardware.

Decision target

To be made during ESH10000654 R1 design (next TA revision). Could be promoted to a please_decision_create once an option is chosen.

Source

DesignLog_Sparrow fixture_electronics.xlsx 2026-05-12 carry-forward entry for the prototype patches.

What is the function of R48 on the Sparrow Test Adapter (ESH10000654 R0)?

R48 was missing on the as-assembled DUT-01 / S/N P0 board and was patched in on 2026-05-15 (see TA patch notice #3). Schematic shows R48 = 0 Ω jumper in the relay-driver area near U1 (74HCS86 EGP10001847) and U2 (TBD62083AFNG,EL).

To answer:

1. Trace R48 in Schematic_Sparrow_TA_R0.pdf — identify the two nets it bridges.
2. Cross-check against the netlist (when QCV / IPC356 / please-netlist-v1.json is generated for project 14).
3. Determine whether R48 is:
   • Critical — required for normal TA operation (e.g. enables a relay-driver output stage). If so, all future ESH10000654 R0 builds must include R48; flag the assembler.
   • Debug/test-point — link used during bring-up only, can stay DNP without operational impact.
   • Calibration — different value for different fixture instances (unlikely given 0 Ω).

Update this question once the role is confirmed and the next-rev BOM is updated accordingly.

Due: 2026-06-15

Symptom

The Sparrow Test Adapter (ESH10000654 R0) schematic lists SN74HCS86PWR (TI quad XOR gate, EGP10000933 in the PLEASE component library) as the manufacturer part number for refdes EGP10001847.

Actual populated IC

CD74HC238PWR (TI 3-line-to-8-line active-HIGH decoder / demultiplexer).

Evidence

The 3-bit-address + enable architecture documented in data/host_aliases/Sparrow_TestAdapter.csv (MPIO00=A0, MPIO01=A2, MPIO08=A1, MPIO09=EN) only makes sense for a 74HC238 — quad XOR gates do not provide 1-of-8 decoding. The relay-routing test fe_J5_vref (PT-PWR.10) drives these MPIOs at 3.3 V to select Y4 → RELAY6_DRV (J5 pin 16 → DMM) and Y5 → RELAY7_DRV (J5 pin 18 → DMM); the relays click as expected when address+EN reach the CD74HC238.

Discovered 2026-05-27 while writing the fe_J5_vref Maestro test in package ESH10000633_SparrowUnitTest_v01 (commit a23f312 / v1.0.234).

Action for TA R1

1. Update schematic mfg-P/N field for refdes EGP10001847 → CD74HC238PWR everywhere it appears.
2. Create the EGP10001847 entry in the PLEASE component library (currently missing — only EGP10000933 / SN74HCS86PWR is registered, but that mpn is wrong here).
3. Verify the BOM line item for EGP10001847 reflects CD74HC238PWR.

Symptom

The FE-board VREF (REF3425 family, 2.500 V ±0.05 % spec) measured at the SDM3055 via the TA relay/Phoenix path reads 2.5096–2.5098 V, consistently across both J5-16 (RELAY6) and J5-18 (RELAY7) routes, on two different SDM3055 units (the in-line meter at 192.168.0.211 reads 2.507, the calibrated meter at 192.168.0.6 reads 2.5097 — the calibrated unit is authoritative).

Reference measurement (truth)

Probed directly across C46 on the FE board (REF3425 output decoupling cap): 2.4996 V — well within REF3425 ±0.05 % (±1.25 mV) initial accuracy.

Magnitude of bias

Routing-path bias: +10.0 ± 0.2 mV (2.5096 − 2.4996). Repeatable across pins, repeatable across the 3-sample readback within each pin (no drift, settled to <0.5 mV per pin within 1 s).

Most likely root cause — ground reference offset on the TA

The SDM3055 measures V(DMM+) − V(DMM−). If TA terminal P4 (DMM−) is not at the same potential as the FE-board AGND that C46 references, the offset adds directly. A 10 mV bias is consistent with ~10 mA of return current flowing through ~1 Ω of shared TA ground impedance.

Update 2026-05-27 (afternoon) — root cause confirmed

Probe check #1 — confirmed. With an ad-hoc wire from SDM3055 ground to FE-board AGND, the same J5 VREF measurement reads:

The ad-hoc ground wire pulled ~7 mV out of the ~10 mV bias — direct evidence that the bulk of the offset is TA ground-reference drift, not REF3425 / DMM / passive contribution.

Additional findings:

• At C46 (FE-board AGND-referenced): 2.4996 V — confirmed in-spec.
• At J5-16 IDC pin (FE side): 2.4995 V — the IDC pin contributes essentially no offset (~0.1 mV).
• Sample-to-sample drift ~1 mV even with the ground wire — characteristic of slowly drifting GND, not measurement noise (SDM3055 on 10 V range normally jitters sub-100 µV).

Architectural root cause — GND pins under test.

On a normal fixture the J4–J9 IDC ground pins would tie the FE board AGND to TA's measurement ground via the ribbon-shield + GND-conductor lines, carrying near-zero current. On this TA, those GND pins are deliberately routed to the host MPIO ADC as signals so they can be measured — so they cannot carry the DMM-return current. The "ground" the SDM3055 sees is whatever potential the TA's local 0 V rail settles at, bridged to FE AGND only through incidental low-impedance paths (cable shield, USB earth, panel chassis). Milliohms of unintended return path → millivolts of drift under any small bias current. The residual ~3 mV after the ad-hoc wire is consistent with thermal EMFs at Phoenix + IDC contacts and the remaining incidental return path.

Resolution

PT-PWR.10 reframed as a routing-path smoke test rather than precision REF verification.

• PT-PWR.10 window widened to 2.490–2.510 V (±0.4 %); passCriterion rewritten to describe the routing-sanity intent.
• Precision verification of VREF remains at PT-PWR.06 (N-Top side, via the on-board ADC chain — N-Top's AGND is the reference there, so no ground-offset problem).
• Hard design rule for TA R1 filed as a separate kind=decision entry on this project: TA R1 must provide a dedicated low-impedance DMM_GND return on the Phoenix terminal block, separate from any J4–J9 GND pin under test.

Closing this question.

Maestro test artifacts

• Test: tests/fe_J5_vref.yaml / python_modules/fe_J5_vref.py
• Package: ESH10000633_SparrowUnitTest_v01
• Linked PLEASE testcase: PT-PWR.10 (id 270) in project 1 (ESH10000633 system).