Sparrow complete product
ESH10000633 · Rev R1
in_progresselectronics
System-level Sparrow product. Test implementation lives in Maestro TAT package ESH10000633_SparrowUnitTest_v01 (https://github.com/esharpab/testdevelopment-esharp-tat-registry-ESH10000633_SparrowUnitTest_v01).
Everything here lives inside a Project (a code + revision, e.g. ESH10000540 R3).
The backbone is the V-model, read top-to-bottom: define what the product must do, plan how to prove it,
execute the proof on real units, then learn from the field — and the Loop closes back up to the top.
This map is live: a block is green with a count when this project actually has that entity,
and dashed/dim when it’s empty. Click any block to open its tab; hover for details.
Arrows are the meaningful links; the implicit “belongs to this Project” edge is left out for legibility.
What each thing means
- Requirement
- One thing the product must do or satisfy — the “what”.
- Test Case
- A defined check that proves one or more requirements — the “how we prove it”. A verified_by trace link ties a test case to the requirement(s) it covers; that link is exactly what Coverage % counts. (So: a test case refers to the requirements it verifies.)
- Verification Plan
- A named grouping of test cases, approved before a test campaign and optionally gated by a milestone.
- Verification Record
- The result of running one test case against one unit: pass / fail / error / na. This is the evidence a requirement is actually met.
- DUT
- Device Under Test — an individual physical unit (by serial number) that records and test data attach to.
- Deviation
- A documented waiver against a verification record (e.g. accept a known non-conformance, with justification).
- Entry
- A knowledge note: a decision (settled choice), notice (assumption / risk / open question), issue (tracked problem), or concept (idea under exploration). It can attach to any other entity.
- Design Rule
- A reusable, checkable engineering constraint. Running the checks turns each violation into a Conflict.
- Conflict
- An open flag raised by a failed design-rule check (or an end-of-life / component-library issue) that needs resolving.
- Milestone
- A dated gate; verification plans can be tied to it.
- Field Issue (RMA)
- A failure reported from the field on a returned unit; Root-Cause Analysis explains why it happened.
- The Loop (S-16)
loop_tracereconciles a field issue against that unit’s own verification record (did it pass at the edge of the band?).closes_looprecords the corrective decision or design rule so the lesson is captured — and clears the project’s open-loop count.- Interface / Port
- A contract between projects; each port can be driven by a requirement (and cascade one into the connected project).
- BOM Component
- A part on this project’s bill of materials, optionally linked to the shared Component Library.
- GRR Study
- A Gauge R&R study measuring how repeatable a test case’s measurement is.
- Test Data
- Production / Maestro run results recorded against DUTs — the population behind a single verification record.
0%
Coverage
0%
Done
0
Requirements
68
Test Cases
13
Open Entries
Timeline
Color = derived gate state · hover a tile for its note.cancelled
Gate 1 — Design Release (all sub-assemblies at Manufacturing in MES; ESH10000634 R3 approved)
cancelled
Gate 2 — Inventory Procurement (all shortfalls resolved; ESH10000182 build order confirmed)
cancelled
Gate 3 — Test & Production Infrastructure (ESH10000654 verified; test procedure complete; DUT serials defined)
cancelled
Gate 4 — First Article (S/N 001 assembled and passed production test)
marker
Schema test
cancelled
Gate 5 — Production Run (20 systems assembled + standalone deliverables 10×636, 20×614, 20×637, 20×EPN1000786)
cancelled
Gate 6 — Delivery (final QC, packaging, delivery documentation complete)
not started
🏁 Release
Status & gates
Chronological — Release is the final gate. Derived & read-only; edit viatrace_milestone_* tools.MS-G1Gate 1 — Design Release (all sub-assemblies at Manufacturing in MES; ESH10000634 R3 approved)
cancelleddue 2026-05-15MS-G2Gate 2 — Inventory Procurement (all shortfalls resolved; ESH10000182 build order confirmed)
cancelleddue 2026-06-05MS-G3Gate 3 — Test & Production Infrastructure (ESH10000654 verified; test procedure complete; DUT serials defined)
cancelleddue 2026-06-05MS-G4Gate 4 — First Article (S/N 001 assembled and passed production test)
cancelleddue 2026-06-12TEST_MILESTONE_TO_CHECK_SCHEMASchema test
markerdue 2026-06-15MS-G5Gate 5 — Production Run (20 systems assembled + standalone deliverables 10×636, 20×614, 20×637, 20×EPN1000786)
cancelleddue 2026-07-06MS-G6Gate 6 — Delivery (final QC, packaging, delivery documentation complete)
cancelleddue 2026-07-13Release / Readiness not started 3/6 met
pending Requirements approved
- PWR-26: draft
- PWR-31: draft
- PWR-12: draft
- PWR-13: draft
- PWR-15: draft
- SIG-14: draft
- SIG-04: draft
- SIG-06: draft
- SIG-05: draft
- SIG-07: draft
pending Coverage ≥ 100%
- No requirements in scope
pending All test cases pass
- 28/68 passed
- 40 not yet run
met
No blocking issues open
met
Deviations resolved
met
Interfaces frozen
Test Cases
28 Pass
0 Fail / Deviated
0 N/A
40 Open10 / 68 Maestro impl.
Coverage — 0.0% · Done — 0.0%
| Code | Title | Category | Coverage | Status |
|---|---|---|---|---|
COM-01 |
I2C Controller end-to-end | Communication | — | — |
COM-02 |
I2C fast-mode operation | Communication | — | — |
COM-03 |
I2C Device EEPROM 24AA02UID | Communication | — | — |
COM-04 |
SPI AD5592R devices accessible | Communication | — | — |
COM-05 |
RS485 full-duplex | Communication | — | — |
COM-06 |
I2C Controller signal levels (EXT_VIO-relative) | Communication | — | — |
COM-07 |
I2C onboard pull-ups + VDDA_SEL coordination | Communication | — | — |
COM-08 |
RS485 differential measurement + electrical limits | Communication | — | — |
COM-09 |
RS485 fault protection + fail-safe bias | Communication | — | — |
COS-01 |
Power LED | Cosmetic | — | — |
COS-02 |
RS-232 LED | Cosmetic | — | — |
COS-03 |
User LEDs (LP5012) respond | Cosmetic | — | — |
FW-01 |
ATmega MCU on I2C | Firmware | — | — |
FW-02 |
IDPROM writable | Firmware | — | — |
PWR-01 |
Common 12V rail | Power | — | — |
PWR-02 |
Common 5V rail | Power | — | — |
PWR-03 |
12V_EXT external rail | Power | — | — |
PWR-04 |
3V3_EXT external rail | Power | — | — |
PWR-05 |
1V8_EXT external rail | Power | — | — |
PWR-06 |
VADJ programmable rail | Power | — | — |
PWR-07 |
EXT_VIO programmable rail | Power | — | — |
PWR-08 |
VREF precision reference | Power | — | — |
PWR-09 |
External rails OCP | Power | — | — |
PWR-10 |
External rail VMEAS accuracy | Power | — | — |
PWR-11 |
External rail IMEAS accuracy | Power | — | — |
PWR-12 |
N-Top +18V rail | Power | — | — |
PWR-13 |
N-Top −18V rail | Power | — | — |
PWR-14 |
PoE input range | Power | — | — |
PWR-15 |
PoE maximum output power | Power | — | — |
PWR-16 |
PoE VMEAS accuracy | Power | — | — |
PWR-17 |
PoE IMEAS accuracy | Power | — | — |
PWR-18 |
Active Load source voltage range | Power | — | — |
PWR-19 |
Active Load sink current (IDC) | Power | — | — |
PWR-20 |
Active Load sink current (Phoenix) | Power | — | — |
PWR-21 |
Active Load energy limit | Power | — | — |
PWR-22 |
Active Load VMEAS accuracy | Power | — | — |
PWR-23 |
Active Load IMEAS accuracy | Power | — | — |
PWR-24 |
PSU (optional) range and accuracy | Power | — | — |
PWR-25 |
Common 12V / 5V rail current protection | Power | — | — |
PWR-26 |
External rail OCP transient blanking + fast-trip | Power | — | — |
PWR-27 |
External rail slew control (SRON) + bleed-out | Power | — | — |
PWR-28 |
PoE Class 1–8 support + 2-pair/4-pair delivery | Power | — | — |
PWR-29 |
PoE polarity indication LED | Power | — | — |
PWR-30 |
PoE port-power limits, classification + protection | Power | — | — |
PWR-31 |
Active Load protection mechanisms | Power | — | — |
REQ-EL-001 |
RoHS Compliance | compliance | — | — |
REQ-EL-002 |
REACH / SVHC Declaration | compliance | — | — |
REQ-EL-003 |
EMC Compliance | compliance | — | — |
REQ-EL-004 |
Operating Temperature Range | environmental | — | — |
REQ-EL-005 |
ESD Protection | robustness | — | — |
REQ-EL-006 |
CE Marking Applicability | compliance | — | — |
REQ-EL-007 |
Test Limit Derivation Documented | quality | — | — |
SIG-01 |
MPIO 0–5 V (4 channels) | Signal | — | — |
SIG-02 |
FE_MPIO OV-protected (12 channels) | Signal | — | — |
SIG-03 |
Differential AIN precision (8 channels) | Signal | — | — |
SIG-04 |
PWM programmable (2 channels) | Signal | — | — |
SIG-05 |
Tach input (2 channels) | Signal | — | — |
SIG-06 |
Relay driver low-side (4 channels) | Signal | — | — |
SIG-07 |
Fixed Load 2.2 kΩ (4 channels) | Signal | — | — |
SIG-08 |
Audio Load (phantom/bias) | Signal | — | — |
SIG-09 |
Tampering latch-and-hold (2 channels) | Signal | — | — |
SIG-10 |
USR_GPIO functional | Signal | — | — |
SIG-11 |
AUDIO_GND ↔ system GND galvanic link | Signal | — | — |
SIG-12 |
MPIO floating-input pulldown | Signal | — | — |
SIG-13 |
FE_MPIO fault-protected analog switches | Signal | — | — |
SIG-14 |
Differential AIN PGA gain settings + auto-scale | Signal | — | — |
SIG-15 |
MPIO/FE_MPIO load constraints for full accuracy | Signal | — | — |
SYS-01 |
Sub-assemblies installed and seated | System | — | — |
SYS-02 |
Fixture Link silkscreen revision marking | System | — | — |
SYS-03 |
Power-on from 20 V DC via Fixture Link eFuse | System | — | — |
SYS-04 |
PoE subsystem accepts 44–57 V isolated input | System | — | — |
SYS-05 |
Sparrow Fixture Electronics PCBA dimensions | System | — | — |
SYS-06 |
Accordion Agent enclosure dimensions | System | — | — |
SYS-07 |
Production test must exercise every user-accessible pin | System | — | — |