Defect

On Sparrow Test Adapter P0, the AIN_P / AIN_N nets are connected to the wrong pins on the J4 IDC connector. The result at runtime is that the N-Top ADC's per-channel differential reads have the opposite sign of the actual bus differential — every channel, every gain, every voltage point.

Confirmed on rig 2026-06-18 (post-GND-patch run a95f55da): with PSU commanded +5 V and POS polarity relay active, the DMM reads +5.0001 V (bus is +V differential as expected) but the N-Top ADC reads −5.005 V (sign inverted, magnitude correct within ~0.1 %). Symmetrically, NEG sweep at PSU=−5 V → DMM=−5.0005 V, ADC=+5.003 V.

Why this cannot be patched

The pin assignment is baked into the TA PCB routing under the J4 connector. There is no jumper or trace-cut workaround that recovers the correct AIN_P / AIN_N polarity at all 8 channels without re-spinning the board.

Test-code workaround (confirmed working end-to-end 2026-06-18)

The fe_J4_analog_high_range test compensates for the pin-swap in two layers:

1. DMM-as-truth with always-negated sign (v1.0.306): the per-channel regression uses truth = -dmm_v regardless of polarity, so the observed slope comes out at +1.0 when magnitude tracks (instead of −1.0 due to pin swap).
2. Per-(channel, gain) cal writeback (v1.0.315+): J4.50 reads the N-Top CALIBRATION blob, applies new_cal_gain = old / slope and new_cal_offset = old − intercept / slope to each ADC_CH_ entry, writes back. The post-cal sweep (J4.62..J4.68) then verifies against the tight ±0.15 % / ±2 mV gates.

Confirmed: Maestro run ec14209d-808a-42cb-be8a-e1a594667e90 (2026-06-18 17:05 UTC, v1.0.319) — all 7 POST-CAL verification sweeps PASS on N-Top S/N A003288 + TA P0. The workaround closes the calibration loop in a single test run.

What to fix in next TA revision (R1+)

• Verify J4 pinout against the N-Top ESH10000535 AIN_P / AIN_N assignment in the schematic; correct the routing so that AIN_P_CH on J4 lands on the N-Top's AIN_P_CH, and same for AIN_N.
• The galvanic GND wire patch logged in E-016 (TA GND ↔ PSU connector GND) ALSO needs to become a designed-in trace on the next TA revision — not a wire patch.
• Once the pin-swap is fixed in hardware, the truth = -dmm_v rule in _sweep_polarity() should be reverted to truth = +dmm_v (or the sign-flip controlled by a board-rev flag) so the same test code works on R0 (negate) and R1+ (no negate).

Both items above should be reviewed together against the J4 footprint at the schematic stage of R1.

Effect on prior entries

• E-016 (P0 GND patch): the GND patch + this workaround together close the original J4 failure path (E-012, withdrawn E-013, and now closed E-014).
• E-014 (single-ended / V/2 clustering): closed today as superseded. The "single-ended ADC" hypothesis was wrong; the real causes were E-016 (GND) + this entry (pin swap).

Reproducibility

• Pre-workaround failure: a95f55da-9aa7-419c-ae9d-9c5b072e0291 (2026-06-18 11:14, v1.0.302+GND-patch on TA P0). CH1_GAIN_DEV_PCT ≈ −200 % across all gains; ADC magnitudes within ~0.1 % of DMM but inverted.
• Sign-flip workaround working, offsets failing: d1961a4f-c796-4cb3-9970-1cd13f895343 (2026-06-18 14:13, v1.0.312). G_1/4 + G_1/2 still failed on offsets pre-cal; G_1..G_16 PASS.
• Full close — cal writeback + post-cal verify all PASS: ec14209d-808a-42cb-be8a-e1a594667e90 (2026-06-18 17:05, v1.0.319).

Symptom

The v1.0.300 CH1-only diagnostic run (3c0c6bab, 2026-06-18 06:54) was designed to discriminate between "TA shorting is incomplete" (sister entry E-013, now withdrawn) and "the ADC read itself is unreliable". Per voltage point it ran: 5× numeric_results.measure(samples=100) → 5× get_value() → 5× numeric_results.measure() → 5× get_value() on CH1 only, holding the bus at a fixed PSU voltage and a fixed polarity-relay state.

Three observations:

1. Within a single block, successive reads bounce between discrete values. At G_1/4 POS +5 V on CH1, the 5 sequential numeric_results.measure() calls returned values clustered around ~0 V, ~+2.5 V, and intermediates — not a tight cluster around any one value. The bus voltage at the DMM was stable at −5.000 V the whole time.
2. numeric_results.measure() and get_value() disagree at the same instant. get_value() tends to land near a "mid-range" smoothed value (averaging the bounce), while numeric_results.measure(samples=N) lands closer to whatever the underlying ADC samples happened to be during that 100-sample window.
3. Values cluster around V/2, not V. Across all the voltages, channels, and runs from 2026-06-17 + 2026-06-18, the ADC magnitudes never approach the bus magnitude — they sit at half. At +5 V bus, ADC reads cluster around +2.5 V; at +12 V, around +6 V; at +18 V, around +9 V.

Diagnosis (engineer-confirmed 2026-06-18)

The N-Top ADC is a single ADC + 8-channel multiplexer running free — not 8 independent differential channels each tied to one AIN_P/AIN_N pair. The driver names (ADC_CH1 … ADC_CH8) suggest 8 independent channels, but underneath, the mux cycles through inputs at its own clock, and any read just snapshots the mux at whatever phase it happens to be in. So:

• numeric_results.measure(target="ADC_CH1", samples=100) does NOT take 100 samples of CH1. It takes 100 samples of the free-running mux stream that happens to be labelled as the CH1 endpoint.
• The 8 different "per-channel" values that were the original symptom for E-013 were the same single ADC catching the free-running mux at 8 different phases — not 8 channels seeing 8 different voltages on a partially-shorted bus.

The V/2 clustering points to a second architectural fact: the ADC reads single-ended of one bus rail (likely AIN_P referenced to AGND), not differentially. With a symmetric ±V drive between AIN_P and AIN_N (PSU+V_psu across the bus, AGND at the bus midpoint), AIN_P sits at +V_psu/2 above AGND. The ADC reads V/2, not V.

Implication for the J4 test design

The whole fe_J4_analog_high_range approach (drive ±V_psu differentially across AIN_P/AIN_N, expect the ADC to read ±V_psu) is built on the assumption of 8 differential ADC channels. If the underlying ADC is single-ended-of-symmetric-bus + multiplexed, that assumption fails on two axes:

1. We can never read V; we read V/2 at best.
2. Per-channel comparison is meaningless — there's no per-channel variation to measure; the variation we see is mux-phase aliasing.

So the test verdicts from yesterday and today on J4 are not just failing on hardware — they're failing on a test premise that doesn't match the hardware. We need an architecture-correct test plan before we can call J4 PASS or FAIL on any unit.

Next steps

1. Confirm the N-Top ADC architecture from the schematic (project 3 — ESH10000535_Sparrow-N-Top-PCBA_R3). Find the actual ADC part, its mux topology, and whether the AIN_P/AIN_N inputs are wired to a true differential front-end or to a single-ended-with-mux front-end.
2. Confirm the AIN_P/AIN_N TA shorting (continuity-test on the bench, per the steps in withdrawn E-013) — independent of the ADC question, so we know what the TA actually does.
3. Redesign the J4 test approach to match the actual architecture:
   • If single-ended + mux: drive each channel's input pin one at a time (not a common bus), and expect a V/2 or V reading per the schematic.
   • If we need to read the bus differentially, do it via the DMM (already in place) — not via the ADC.
4. Update the test docstring to stop describing 8 differential channels if the hardware is mux + single-ended.

Cross-references

• Withdrawn sister entry on this project: E-013 (TA shorting interpretation that this entry supersedes).
• Open sister entry on this project: E-012 (J4 polarity relays don't flip — now strictly DMM-evidence-based).
• N-Top hardware project: ESH10000535_Sparrow-N-Top-PCBA_R3 (projectId 3) — the schematic-side investigation in step 1 above lives there.

Reproducibility

• daf8fced (v1.0.298, 2026-06-17 18:00) and a3bc238b (v1.0.297-era, 2026-06-17 17:54) — full 8-channel sweeps; raw step_results JSON in C:\Workspace\PLEASE-projects\ESH10000633_Sparrow-complete-product_R1\04_Verification\J4_runs_2026-06-17\.
• 3c0c6bab (v1.0.300, 2026-06-18 06:54) — CH1-only NR/GV/NR/GV diagnostic that overturned the per-channel interpretation. Maestro report DB has been re-populated post-migration; this run is queryable.

Update 2026-06-18 — DMM evidence stands; ADC evidence does not

After the v1.0.300 CH1-only diagnostic run (3c0c6bab, 06:54) revealed the N-Top ADC architecture (single ADC + 8-channel mux running free — sister issue filed today), the standing evidence for this entry needs to be re-classified:

• DMM evidence still stands and is authoritative. The DMM is a self-contained 6½-digit instrument reading the AIN_P/AIN_N bus directly via the fixed coupling relay. Across both 2026-06-17 runs, with PSU always commanded as +V, the DMM reads the same polarity (negative magnitude) regardless of whether ANALOG_POS (Y0) or ANALOG_NEG (Y1) is energised. The DMM cannot be deceived by N-Top ADC mux behaviour. The polarity relays not flipping the bus remains the most likely diagnosis.
• ADC-side evidence is unreliable for this question. I had also pointed to "all ADC readings positive even for NEG sweeps" as corroborating evidence. That's not load-bearing — because the N-Top ADC reads single-ended of one bus rail (cluster around V/2 regardless of differential polarity), per-channel ADC values cannot independently distinguish POS from NEG. Even with the polarity relays working perfectly, the ADC values would look similar.

So the diagnosis narrows: the DMM evidence is what we trust, and the bench investigation steps below (scope the differential at ADC+/ADC− while toggling addresses 0 and 1; check coil/contact integrity of the two reed relays) are the right next step.

The v1.0.299 firmware-side defence (strict 3-step decoder sequencing EN-LOW → set A → EN-HIGH) is still worth keeping. If a bench probe confirms the contacts do flip mechanically but the bus doesn't flip electrically, suspect the contact wiring; if the contacts themselves don't actuate for Y1, suspect a dead reed coil.

(original body, preserved)

Symptom

During J4 bipolar sweep on Sparrow Unit Test (fe_J4_analog_high_range, project 1), with the PSU always commanded as a positive voltage, the DMM (on the AIN_P/N bus via the diode-OR-to-DMM-coupling relay) reads the same polarity regardless of whether ANALOG_POS (Y0, address 0) or ANALOG_NEG (Y1, address 1) is energised.

Per the test-adapter topology (engineer-described 2026-06-17):

• PSU → 2 polarity relays. One position: PSU+ → ADC+, PSU− → ADC−. Flipped: PSU+ → ADC−, PSU− → ADC+.
• ADC+/ADC− → fixed (non-flipping) coupling relay → DMM+/DMM−.
• ADC+/ADC− → 8 individual ADC channels via TA shorting.

So with PSU always +V_psu, the DMM should:

• POS: read +V_psu (DMM+ on ADC+ which carries PSU+)
• NEG: read −V_psu (PSU+ now on ADC−, so DMM sees the reverse)

What we see instead, across two independent runs (daf8fced 18:00 and a3bc238b 17:54 on 2026-06-17):

(* a3bc238b is an earlier version where DMM didn't have time to settle on high-V points; daf8fced (v1.0.298) waits for DMM settle and gets clean ±0 mV deviation from |PSU set|.)

DMM reads the same sign for both POS and NEG. Magnitude tracks PSU command correctly.

Implication

Per the engineer-described topology, the only way for DMM sign to NOT change between POS and NEG is for the polarity relays to NOT actually flip the bus. Either:

1. ANALOG_NEG (Y1) reed relay is dead — its coil energises (the decoder Y1 line goes HIGH, address mapping confirmed by E-024 on project 1) but the contacts don't close. ANALOG_POS contacts remain whatever they were, so the bus stays in POS configuration regardless.
2. ANALOG_NEG contacts are wired identically to ANALOG_POS (mechanical / PCB error) — both relays close the same connection (PSU+ → ADC+).
3. Both relays close together for the NEG address — would short PSU+ to PSU− on the ADC bus, but the DMM reads ±V cleanly so this is less likely.

Bench investigation

1. Probe the differential at ADC+ / ADC− directly (not via DMM) while toggling addresses 0 and 1.
2. Check continuity / coil resistance of the two polarity reed relays.
3. Visually inspect the relay contacts and trace routing on the TA.

Test-code-side defence already added

Maestro package v1.0.299 (commit 351fe33) split _activate_j4_relay into a strict 3-step sequence — explicit EN-LOW → set A0/A1/A2 → EN-HIGH — to defend against any atomic-set_values ordering glitch in the host firmware. If the next J4 run (v1.0.300+) shows the polarity actually flipping now, the issue was SW-side and this entry can be downgraded to a near-miss / closed. If it still doesn't flip, the hardware diagnosis above applies.

Reproducibility

Reproducible across every J4 run on 2026-06-17 from v1.0.295 onward. Raw step_results JSON salvaged to C:\Workspace\PLEASE-projects\ESH10000633_Sparrow-complete-product_R1\04_Verification\J4_runs_2026-06-17\.

WITHDRAWN 2026-06-18 — superseded by N-Top ADC architecture issue

The per-channel ADC divergence reported below is not evidence that TA AIN_P/N shorting is incomplete. The v1.0.300 CH1-only diagnostic run (3c0c6bab, 2026-06-18 06:54) showed that on a single channel:

• Successive numeric_results.measure() calls return wildly different values (bounce between ~0, ~2.5, intermediates).
• numeric_results.measure() and get_value() disagree at the same instant.
• Values cluster around V/2, never approach V.

Per the engineer (2026-06-18), the N-Top ADC is a single ADC + 8-channel multiplexer running free — not 8 independent differential channels. numeric_results.measure(target="ADC_CH1", samples=100) samples whatever the mux happens to point at, not 100 samples of CH1 specifically. The 8 different "per-channel" values in the original symptom were the same single ADC catching the free-running mux at 8 different phases, not 8 channels seeing different voltages on a partially-shorted bus.

The TA shorting may be perfectly fine. We cannot diagnose it via per-channel ADC reads on a free-running mux. The proper test approach has to be rebuilt around the actual ADC architecture — tracked in the new sister entry filed today on this project.

The bench investigation steps below (continuity-test the AIN_P/N shorting) are still worth doing as independent TA sanity checks, just not as a response to the ADC divergence symptom.

(original body, preserved for history)

Symptom

Per the fe_J4_analog_high_range docstring (and the TA design intent):

"The Sparrow Test Adapter (ESH10000654 R0) shorts all 8 AIN_P pins to one common bus and all 8 AIN_N pins to another common bus."

If that's true, all 8 N-Top ADC channels should read the same differential when the bus is energised at a fixed voltage. In practice they don't.

Data from run daf8fced 2026-06-17 18:00 (v1.0.298), J4.02 sweep at G_1/4:

                            CH1     CH2     CH3     CH4     CH5     CH6     CH7     CH8
POS +5 V    ADC[1..8] =  +1.213  -0.045  -0.047  -0.046  +2.557  +2.558  +0.198  +2.563
POS +12 V   ADC[1..8] =  +3.248  +6.085  +4.796  +6.152  +1.743  +4.665  +6.019  +1.601
POS +18 V   ADC[1..8] =  +9.095  +5.644  +8.254  +8.761  +9.067 +10.204  +8.761  +7.002
NEG +5 V    ADC[1..8] =  -0.046  +2.487  +0.053  +2.580  +2.245  +0.081  +0.064  -0.127
NEG +12 V   ADC[1..8] =  +6.095  +6.008  +5.101  +4.763  +5.992  +6.056  +4.469  +5.250
NEG +18 V   ADC[1..8] =  +8.116  +5.501  +9.069  +7.290  +8.810  +7.347  +9.151  +4.858

At POS +5 V we see CH2/3/4/7 ≈ 0 V and CH1/5/6/8 ≈ 1–2.5 V. The DMM on the same bus reads ~−5 V cleanly (bus IS energised). So the bus voltage exists, but only some channels see it.

Two suspicious patterns (original interpretation — now superseded)

1. All ADC readings are positive even for NEG sweeps — interpreted as polarity not flipping. Sister issue E-012 still tracks this from the DMM side.
2. Recurring 2.5 V on some channels — initially attributed to floating-input coupling to the REF3425 VREF. Now understood to be the V/2 signature of single-ended reads on a symmetric bus, not floating channels.

Bench investigation (still worth doing as TA sanity checks)

1. Continuity test from AIN_P pin of CH1 to AIN_P pins of CH2..CH8 at the TA's J4 connector — should all read short (≤ 1 Ω). Likewise for AIN_N.
2. Continuity from each AIN_P / AIN_N to the ADC+/ADC− nodes where the polarity relays route.
3. Visual inspect the TA J4 routing for missing shorting nets.

Reproducibility

Original divergence pattern observable in both 2026-06-17 runs (daf8fced, a3bc238b). Raw step_results JSON salvaged to C:\Workspace\PLEASE-projects\ESH10000633_Sparrow-complete-product_R1\04_Verification\J4_runs_2026-06-17\. CH1-only follow-up that overturned the interpretation: run 3c0c6bab, 2026-06-18 06:54, v1.0.300.

Context

Discovered while measuring FE-board VREF (REF3425, 2.500 V ±0.05 %) through the Sparrow Test Adapter R0 to an external Siglent SDM3055 DMM via Phoenix terminals P3 (DMM+) / P4 (DMM−). See linked test case PT-PWR.10 (id 270, project 1) and the resolved question E-007 (id 54) on this project for the diagnostic chain.

Problem

TA R0 has no dedicated low-impedance ground return between the DUT board AGND and the Phoenix terminal block's DMM− pin. The J4–J9 IDC ground pins on TA R0 are deliberately routed to the host MPIO ADC as signals, so they cannot carry return current. As a consequence, the TA's local 0 V rail sits at a +5 to +15 mV bias relative to the DUT's AGND, depending on incidental cable / chassis paths. Any precision DMM measurement via the TA Phoenix terminals inherits this bias.

Practical effect: PT-PWR.10 cannot be a precision check of REF3425; only PT-PWR.06 (N-Top-internal ADC chain) verifies the 2.500 V ±0.05 % spec.

Decision

Each J-connector that exposes a DUT GND pin shall provide a populatable jumper that bonds that GND pin to TA's measurement ground. The jumper preserves the existing "GND pin as host-measurable signal" capability when unpopulated, and enables precision DMM measurement when populated. The two modes are mutually exclusive by design.

Per-connector jumper

• J5 — required minimum. Bonds J5 GND to TA AGND when populated, providing the low-impedance return for the FE VREF precision measurement (PT-PWR.10) and any future precision DMM tests routed via J5.
• J4, J6, J7, J8, J9 — strongly recommended to apply the same pattern, so any J-connector can be the precision-measurement source without ad-hoc workarounds. Defer per-connector inclusion to TA R1 layout review based on which connectors host precision-measurement targets in the current verification plan; bias toward "include all" to avoid an R2 revisit.

Operator contract

• Before any DMM-based precision measurement: populate the jumper on the J-connector being measured.
• After the precision measurement: remove the jumper, so the GND-continuity check on host MPIO still verifies the DUT-side GND propagation through the IDC connector (which is what that test is for — a populated jumper would just measure TA's local GND, not the DUT path).

Jumper-state sensing (recommended)

Add an MPIO sense net per jumper (high-impedance pull-up on TA, low on the jumper-down side) that reads HIGH when the jumper is populated. The Maestro test framework can then:

• Refuse to start a precision DMM measurement if the relevant jumper is not populated → turns a silent ground-bias error into a hard fail with a clear operator-facing message.
• Refuse to start a GND-continuity check if any jumper is populated → prevents an operator from accidentally "passing" the continuity check via the jumper rather than the DUT path.

Test sequencing

Production flow should not require operator intervention mid-run. Two acceptable patterns:

1. GND-continuity tests run first (jumpers unpopulated). Pause with operator prompt. Jumpers populated. Precision DMM tests run. Pause. Jumpers removed. Remaining tests run.
2. Precision DMM tests are diagnostic-only (not part of standard production), invoked manually as a calibration / acceptance step. Standard production keeps jumpers unpopulated; precision tests are operator-driven sessions with the jumper present.

The PT-PWR.10 routing smoke test (current widened window 2.490–2.510 V) remains valid in either mode.

Phoenix DMM− still required

The Phoenix terminal block's DMM− pin must reach TA AGND via 0-Ω strap, chassis bond, or dedicated header — see the original two options below. The per-connector jumpers complete the DUT→TA path; the Phoenix DMM− completes the TA→DMM path. Both halves are necessary.

Acceptable Phoenix-side implementations (carried over from the original draft):

1. A dedicated GND pin (e.g. PHX_GND / DMM_GND) on the Phoenix terminal block, wired directly to the TA's GND plane via a 0-Ω strap and brought out as a single hard-wired return.
2. The Phoenix terminal block's mounting screws / chassis tied to the TA GND plane, allowing the DMM− cable to bond via a short stub.

Cable reach

The Phoenix DMM− must be reachable by a short cable (≤ 30 cm) so it can be used by all external DMM measurements (precision + general-purpose).

Why this matters

Without this, any precision DMM-based measurement via the TA is limited to roughly ±15 mV resolution after bias subtraction, which is insufficient for verifying:

• VREF precision references (REF3425 / REF3425A spec ±1.25 / ±2.5 mV)
• Power-rail accuracy claims tighter than ±10 mV
• High-resolution ADC linearity tests routed via TA to an external DMM

Workaround for TA R0

An ad-hoc wire from SDM3055 ground to FE-board AGND reduces the bias from ~10 mV to ~3 mV (probe check #1 in E-007). Acceptable for the current PT-PWR.10 routing smoke test (window widened to ±0.4 %), but not a substitute for the TA R1 fix.

Related artifacts

• Question entry: E-007 on this project (id 54) — diagnostic chain + resolution.
• Schematic-bug entry: E-006 on this project (id 53) — also fix in TA R1.
• Test case: PT-PWR.10 (id 270) on project 1.
• Maestro implementation: tests/fe_J5_vref.yaml in ESH10000633_SparrowUnitTest_v01.

Context

The audio loopback test PT-SIG.04 (MIC_BIAS / Audio Load) uses a DSUB-9 loopback plug fitted with 680 Ω pull-ups to 2.5 V on each MIC_IN line. The 680 Ω + the FE board's switched 2.2 kΩ load form a voltage divider whose mid-point at MIC_IN reports ≈ 1.910 V when the FE-side load is asserted; the YAML window 1.86 V ≤ V_MIC ≤ 1.95 V corresponds to R_bias varying ±2.5 % around 2.2 kΩ (matches SIG-08 acceptance RLOAD_BIAS 2156–2264 Ω).

On Sparrow Test Adapter R0, the 2.5 V supply for the loopback plug must come from somewhere external — typically an ad-hoc bench supply or a hand-wired tap off a nearby reference. There is no defined TA → loopback-plug power path.

Decision

TA R1 shall provide a dedicated 2.5 V + GND output connector, intended to feed the DSUB-9 audio loopback plug.

Acceptable implementations:

1. A 2-pin header (e.g. 2.54 mm pitch) labelled DSUB_VREF_OUT / GND, wired to a buffered 2.5 V source on TA.
2. A small Phoenix-style screw-terminal pair, similarly labelled.

The connector shall sit physically near the J6 / DSUB-9 routing area so a short jumper cable can reach the DSUB loopback plug without crossing the precision-measurement paths.

Source for the 2.5 V

Two acceptable sources on TA R1:

1. Dedicated buffered reference on TA — e.g. a REF3425 (±0.05 %) followed by a unity-gain op-amp buffer with adequate output drive. Cleanest electrical option; isolates the loopback load from any other precision-reference user on TA and decouples this output from the boards-under-test.
2. Tap of an existing TA reference, brought out via dedicated wiring (not via any J-connector IDC path which is under test).

Option 1 is preferred — keeps the TA self-sufficient for this measurement chain and avoids cross-coupling fixture state to the boards-under-test.

Output drive budget

Worst-case sink for the loopback plug: 4 MIC_IN lines, each pulling ≈ 0.87 mA through their 680 Ω pull-up when the FE-side R_bias load is engaged → total ≤ ~3.5 mA simultaneous. Pick a 2.5 V source rated ≥ 10 mA with low output impedance (≤ 1 Ω) to ensure < 5 mV droop under load, which keeps the loopback divider within the existing ±2.5 % window.

Why this matters

• Eliminates the ad-hoc external-supply dependency for PT-SIG.04 on the bench.
• Makes the test self-contained: a tester running PT-SIG.04 needs only the TA + the DSUB loopback plug, no external 2.5 V supply.
• Improves repeatability: a TA-sourced 2.5 V is one well-characterised quantity per fixture; "whatever bench supply happened to be at hand" is not.
• Removes a possible silent-failure mode (operator forgot to attach the bench supply, loopback reads 0 V, test still appears to run but bias measurement is meaningless).

Considerations / open

• Labelling on TA silkscreen must make the polarity and voltage unambiguous so an operator cannot accidentally short the loopback's 5 V mic-supply line into the 2.5 V output.
• Should there be a sense / monitor net that reads back the 2.5 V output via a host MPIO ADC channel? If yes, the Maestro test framework can refuse to start PT-SIG.04 if the output is missing or out of spec. Worth ~1 MPIO channel; recommended.
• DSUB loopback plug revision: this decision implies a matched revision of the loopback plug accessory that uses the TA-provided 2.5 V rather than an external supply. Track separately or note in the loopback plug BOM.

Related artifacts

• Test case: PT-SIG.04 (id 28) on project 1 — Audio Load / MIC_BIAS test, currently status=pass in PLEASE with the ad-hoc external 2.5 V supply.
• Requirement: SIG-08 (Audio Load) — describes the MIC_BIAS sourcing spec the loopback test verifies.
• Maestro implementation: tests/fe_J6_audio.yaml in ESH10000633_SparrowUnitTest_v01.
• Companion TA R1 decisions: E-008 (per-J-connector DMM_GND jumpers), E-006 (schematic mfg P/N fix on EGP10001847).

Decision

For Sparrow Test Adapter R1, route a dedicated low-impedance ground return from the DUT (FE-board AGND) to Phoenix terminal P4 (DMM−). This return must not share path with the J4–J9 IDC GND pins (which are deliberately routed to host MPIO ADC channels as measurable signals on R0 and so cannot carry the DMM-return current).

Why

Confirmed via empirical probing 2026-05-27 (calibrated SDM3055 at 192.168.0.6):

The ad-hoc wire test cuts the bias from +10 mV to +3 mV — direct confirmation that the dominant error source is a shared-ground impedance bias, not the relay matrix or the SDM3055 calibration. A dedicated AGND return clears the bulk of the offset; the residual ~3 mV is plausibly fixture-cable / chassis loop pickup, addressable later if needed.

Path forward

1. Add DMM_GND net on TA R1 schematic — dedicated trace from a clean AGND star point on the test-adapter side back to Phoenix P4.
2. Verify routing has no shared current path with any signal return (especially the J4–J9 IDC GND-monitored pins).
3. Re-measure PT-PWR.10 on the prototyped R1 and confirm the readback at TA matches C46 within REF3425 ±0.05 % (±1.25 mV).
4. Tighten tests/fe_J5_vref.yaml window back from ±10 mV → ±2 mV once the R1 fix is verified.

Resolves

PLEASE entry E-007 on project 14 (root cause investigation). PT-PWR.10 window stays widened to ±10 mV (tests/fe_J5_vref.yaml v1.0.235) until R1 lands.

Maestro test artifacts referenced

• tests/fe_J5_vref.yaml — measurement-window docstring documents the bias and references this entry.
• Linked PLEASE testcase: PT-PWR.10 (id 270) in project 1.

Findings (engineer bench, 2026-06-18)

Two independent corrections to how the test code drives the TA address mux (0.8.ESH10000568.MPIO00_RELAY_A0 / MPIO08_RELAY_A1 / MPIO01_RELAY_A2 / MPIO09_RELAY_EN), both discovered via direct bench probing:

1. Drive level: 5 V active (not 3.3 V)

The MPIO signals feed a 5V-powered address mux (the CD74HC238 on the TA; refdes EGP10001847). The mux outputs drive the reed-relay coils directly — there's no separate coil driver between the mux output and the coil. So the input drive level needs to swing the full 5V rail to make the mux output reliably pull each coil to its closure threshold.

The previous _DRIVE_HIGH_V = "3.3000" was insufficient: at 3.3V the mux still switched but its output couldn't reliably pull the coil in, so the downstream reed relays either didn't actuate, intermittently actuated, or got stuck in whatever state they happened to be in. This is what was causing all the J4 / J5_vref / J8_active_load polarity / address-routing weirdness from 2026-06-17.

(Earlier note in this entry speculated about a VCC mismatch / over-voltage concern based on an outdated comment in fe_J5_vref.py that claimed "decoder VCC = 3.3 V per TA R0 schematic". That comment was wrong — the mux is 5V-powered, so 5V drive is correct and within spec, not over-voltage. The misleading comment has been corrected in v1.0.302.)

2. J4 POS/NEG address mapping was inverted

Bench observation with A1=A2=0V and EN=5V:

The code previously had _J4_POS_ADDR = 0 (Y0) and _J4_NEG_ADDR = 1 (Y1). That was a guess from 2026-06-05 made before we knew the 3.3V drive was the underlying failure mode — the "POS configuration confirmed on rig" observation was unreliable because the relays weren't reliably switching. Now bench-confirmed inverted: Y1=POS, Y0=NEG.

The MPIO bit ↔ address mapping is correct as-is in the code and host_aliases/Sparrow_TestAdapter.csv:

(MPIO01 is correctly A2, MPIO02 is J9_EXT_VIO_7 — verified against the CSV.)

Code changes applied

Maestro package v1.0.301 (committed 54f87dd):

• python_modules/fe_J4_analog_high_range.py:
  • _DRIVE_HIGH_V = "5.0000" (was "3.3000")
  • _J4_POS_ADDR = 1 (was 0), _J4_NEG_ADDR = 0 (was 1)
  • Docstring + inline-comment Y0/Y1 ↔ POS/NEG labels updated to match bench reality.
• python_modules/fe_J5_vref.py: _DRIVE_HIGH_V = "5.0000" (was "3.3000").
• python_modules/fe_J8_active_load.py: _DRIVE_HIGH_V = "5.0000" (was "3.3000").

v1.0.302 (doc-only follow-up): rewrote the comment blocks around the _DRIVE_HIGH_V definitions in all three files to reflect the actual topology (5V-powered mux whose outputs drive the coils directly) and remove the earlier speculation about VCC mismatch / over-voltage.

No other Python files drive these MPIO signals. The fe_J5_mpio.py file references MPIO00..03 but on a different module (N-Top ESH10000535, not the TA address mux ESH10000568) — unaffected.

Implications for prior entries

• E-012 (J4 polarity relays don't flip): root-caused — relays DO flip, but only with 5V drive AND correct Y_n label assignment. Closed today, disposition confirmed_defect.
• E-014 (N-Top ADC reads single-ended of one bus rail; values cluster at V/2): unaffected. That's a separate ADC-architecture question independent of the polarity / drive-voltage fix. Stays open.
• E-013 (TA AIN_P/N shorting incomplete): stays withdrawn. Now we'll be able to re-test cleanly with working polarity, but the root mechanism (single ADC + 8-ch mux running free, per E-014) means per-channel comparison still won't be meaningful without a test redesign.

Follow-up

Re-run J4 with v1.0.302 to confirm: (a) DMM flips polarity correctly between POS and NEG sweeps, and (b) per-channel ADC reads at least flip sign on the POS/NEG split, even if the V/2 magnitude question (E-014) remains.

Applied 2026-05-15 to DUT-01 (S/N P0). Not present in ESH10000654 R0 schematic.

What

Tied four J7 nets together onto a single rail (Rail A):

• FE_MPIO_8
• FE_MPIO_10
• RELAY1
• RELAY3

Plus added a 10 kΩ 5 % pull-up to 2.5 V on the rail.

Why

Prototype implementation of next-revision relay-driver readback. The carry-forward originates in ESH10000540/R3/02_Implementation/DesignFiles/DesignLog_Sparrow fixture_electronics.xlsx 2026-05-12.

Coarse-grained limitation

This 2-rail ganged version cannot distinguish which odd-indexed relay fired:

• RELAY1 closed → Rail A goes low (but so does it for RELAY3)
• RELAY3 closed → Rail A goes low (indistinguishable from RELAY1)

Same coarseness for FE_MPIO_8 vs FE_MPIO_10.

Original design intent was 4-channel per-relay readback; that's deferred to next rev (see notice "Next-rev relay-pin fix decision").

Test impact

This patch IS the topology that fe_J7_mpio_relay.yaml Step 2 ("FE_MPIO + RELAY fabric") depends on. Without the patch, the fabric step would produce floating readings.

Components added by patch

• Pull-up resistor: 10 kΩ ±5 % (not in BOM — added physically; suggest tracking as EGP10000097 for any future order if 1 % is acceptable)
• Wire-wraps / jumper wires tying the four J7 pins to the rail node

Applied 2026-05-15 to DUT-01 (S/N P0). Not present in ESH10000654 R0 schematic.

What

Tied four J7 nets together onto a single rail (Rail B):

• FE_MPIO_9
• FE_MPIO_11
• RELAY2
• RELAY4

Plus added a 10 kΩ 5 % pull-up to 2.5 V on the rail.

Why

Same as patch #1 — prototype next-revision relay-driver readback. Even-indexed pair this time.

Coarse-grained limitation

Cannot distinguish:

• RELAY2 vs RELAY4 firing on Rail B
• FE_MPIO_9 vs FE_MPIO_11 driving

Test impact

Co-required with patch #1 for fe_J7_mpio_relay.yaml Step 2. Without the patch, FE_MPIO_9/11 and RELAY2/4 readings would float on the test fixture.

Components added by patch

• Pull-up resistor: 10 kΩ ±5 % (same note as patch #1 re BOM tracking)
• Wire-wraps / jumper wires

Applied 2026-05-15 to DUT-01 (S/N P0).

What

R48 was missing on the as-assembled board — present in schematic, not fitted at assembly. Patched in 2026-05-15.

Schematic value

0 Ω jumper (per Sparrow_TA_R0.pdf — schematic shows R48 as a 0 Ω link in the relay-driver area near U2 TBD62083 / U1 74HCS86).

Why patched

R0 assembly/BOM defect — restore intended schematic functionality. Original schematic was correct; assembler did not mount R48 (likely a placement-list omission, not a deliberate DNP). Patch returns the board to the as-designed state.

⚠️ Open — function TBD

The specific net function of R48 has not been confirmed. From the schematic R48 is a 0 Ω in the relay-driver enable / output area, but the exact role (which signal it links) needs a careful trace of the schematic and netlist. Tracked as Q-TA-01 (separate question entity).

Severity = warning until Q-TA-01 is answered: if R48 turns out to be critical for one of the test-rig functions (e.g. enabling a relay-driver output stage that the production-test depends on), then only patched units can be used. If R48 is purely a debug / test-point link, lesser impact.

Action items

1. Trace R48 from schematic + NetList_Sparrow_TA_R0.qcv (when netlist export is added to project 14's DesignFiles) to confirm net role.
2. Update next-rev BOM to ensure R48 is mounted by the assembler (no longer DNP).
3. If a future production order of ESH10000654 R0 is placed without this patch, flag for rework before the board is used as a test adapter.

Context

The current TA patches #1 + #2 (DUT-01 / S/N P0, 2026-05-15) implement a 2-rail ganged relay-driver readback:

• Rail A = FE_MPIO_8, FE_MPIO_10, RELAY1, RELAY3 + 10K pull-up to 2.5 V
• Rail B = FE_MPIO_9, FE_MPIO_11, RELAY2, RELAY4 + 10K pull-up to 2.5 V

This is coarser than the original 4-channel intent — cannot distinguish RELAY1 vs RELAY3 on Rail A, nor RELAY2 vs RELAY4 on Rail B.

What needs to be decided for next TA revision

How to provide per-relay readback so that any single relay firing can be unambiguously identified by the host-side MPIO reading.

Candidate approaches (sketch — pick one for the next-rev design review):

1. 4 separate rails, each with one MPIO + one RELAY + dedicated pull-up. Cleanest; uses 8 host-MPIO channels (4 sense + 4 unchanged), but only 4 effective.
2. Voltage-divider encoding — each relay drops the rail to a different voltage (e.g. via different in-line series resistors). Uses fewer host MPIOs but is fragile to drift.
3. Time-multiplexed enable — only fire one relay at a time during the test step, so even the ganged rail unambiguously identifies which one. Software-only fix, no TA change.

Option 3 is the lowest-effort fix and probably right for production test. Worth confirming before spending a TA revision on hardware.

Decision target

To be made during ESH10000654 R1 design (next TA revision). Could be promoted to a please_decision_create once an option is chosen.

Source

DesignLog_Sparrow fixture_electronics.xlsx 2026-05-12 carry-forward entry for the prototype patches.

What is the function of R48 on the Sparrow Test Adapter (ESH10000654 R0)?

R48 was missing on the as-assembled DUT-01 / S/N P0 board and was patched in on 2026-05-15 (see TA patch notice #3). Schematic shows R48 = 0 Ω jumper in the relay-driver area near U1 (74HCS86 EGP10001847) and U2 (TBD62083AFNG,EL).

To answer:

1. Trace R48 in Schematic_Sparrow_TA_R0.pdf — identify the two nets it bridges.
2. Cross-check against the netlist (when QCV / IPC356 / please-netlist-v1.json is generated for project 14).
3. Determine whether R48 is:
   • Critical — required for normal TA operation (e.g. enables a relay-driver output stage). If so, all future ESH10000654 R0 builds must include R48; flag the assembler.
   • Debug/test-point — link used during bring-up only, can stay DNP without operational impact.
   • Calibration — different value for different fixture instances (unlikely given 0 Ω).

Update this question once the role is confirmed and the next-rev BOM is updated accordingly.

Due: 2026-06-15

Symptom

The Sparrow Test Adapter (ESH10000654 R0) schematic lists SN74HCS86PWR (TI quad XOR gate, EGP10000933 in the PLEASE component library) as the manufacturer part number for refdes EGP10001847.

Actual populated IC

CD74HC238PWR (TI 3-line-to-8-line active-HIGH decoder / demultiplexer).

Evidence

The 3-bit-address + enable architecture documented in data/host_aliases/Sparrow_TestAdapter.csv (MPIO00=A0, MPIO01=A2, MPIO08=A1, MPIO09=EN) only makes sense for a 74HC238 — quad XOR gates do not provide 1-of-8 decoding. The relay-routing test fe_J5_vref (PT-PWR.10) drives these MPIOs at 3.3 V to select Y4 → RELAY6_DRV (J5 pin 16 → DMM) and Y5 → RELAY7_DRV (J5 pin 18 → DMM); the relays click as expected when address+EN reach the CD74HC238.

Discovered 2026-05-27 while writing the fe_J5_vref Maestro test in package ESH10000633_SparrowUnitTest_v01 (commit a23f312 / v1.0.234).

Action for TA R1

1. Update schematic mfg-P/N field for refdes EGP10001847 → CD74HC238PWR everywhere it appears.
2. Create the EGP10001847 entry in the PLEASE component library (currently missing — only EGP10000933 / SN74HCS86PWR is registered, but that mpn is wrong here).
3. Verify the BOM line item for EGP10001847 reflects CD74HC238PWR.

Symptom

The FE-board VREF (REF3425 family, 2.500 V ±0.05 % spec) measured at the SDM3055 via the TA relay/Phoenix path reads 2.5096–2.5098 V, consistently across both J5-16 (RELAY6) and J5-18 (RELAY7) routes, on two different SDM3055 units (the in-line meter at 192.168.0.211 reads 2.507, the calibrated meter at 192.168.0.6 reads 2.5097 — the calibrated unit is authoritative).

Reference measurement (truth)

Probed directly across C46 on the FE board (REF3425 output decoupling cap): 2.4996 V — well within REF3425 ±0.05 % (±1.25 mV) initial accuracy.

Magnitude of bias

Routing-path bias: +10.0 ± 0.2 mV (2.5096 − 2.4996). Repeatable across pins, repeatable across the 3-sample readback within each pin (no drift, settled to <0.5 mV per pin within 1 s).

Most likely root cause — ground reference offset on the TA

The SDM3055 measures V(DMM+) − V(DMM−). If TA terminal P4 (DMM−) is not at the same potential as the FE-board AGND that C46 references, the offset adds directly. A 10 mV bias is consistent with ~10 mA of return current flowing through ~1 Ω of shared TA ground impedance.

Update 2026-05-27 (afternoon) — root cause confirmed

Probe check #1 — confirmed. With an ad-hoc wire from SDM3055 ground to FE-board AGND, the same J5 VREF measurement reads:

The ad-hoc ground wire pulled ~7 mV out of the ~10 mV bias — direct evidence that the bulk of the offset is TA ground-reference drift, not REF3425 / DMM / passive contribution.

Additional findings:

• At C46 (FE-board AGND-referenced): 2.4996 V — confirmed in-spec.
• At J5-16 IDC pin (FE side): 2.4995 V — the IDC pin contributes essentially no offset (~0.1 mV).
• Sample-to-sample drift ~1 mV even with the ground wire — characteristic of slowly drifting GND, not measurement noise (SDM3055 on 10 V range normally jitters sub-100 µV).

Architectural root cause — GND pins under test.

On a normal fixture the J4–J9 IDC ground pins would tie the FE board AGND to TA's measurement ground via the ribbon-shield + GND-conductor lines, carrying near-zero current. On this TA, those GND pins are deliberately routed to the host MPIO ADC as signals so they can be measured — so they cannot carry the DMM-return current. The "ground" the SDM3055 sees is whatever potential the TA's local 0 V rail settles at, bridged to FE AGND only through incidental low-impedance paths (cable shield, USB earth, panel chassis). Milliohms of unintended return path → millivolts of drift under any small bias current. The residual ~3 mV after the ad-hoc wire is consistent with thermal EMFs at Phoenix + IDC contacts and the remaining incidental return path.

Resolution

PT-PWR.10 reframed as a routing-path smoke test rather than precision REF verification.

• PT-PWR.10 window widened to 2.490–2.510 V (±0.4 %); passCriterion rewritten to describe the routing-sanity intent.
• Precision verification of VREF remains at PT-PWR.06 (N-Top side, via the on-board ADC chain — N-Top's AGND is the reference there, so no ground-offset problem).
• Hard design rule for TA R1 filed as a separate kind=decision entry on this project: TA R1 must provide a dedicated low-impedance DMM_GND return on the Phoenix terminal block, separate from any J4–J9 GND pin under test.

Closing this question.

Maestro test artifacts

• Test: tests/fe_J5_vref.yaml / python_modules/fe_J5_vref.py
• Package: ESH10000633_SparrowUnitTest_v01
• Linked PLEASE testcase: PT-PWR.10 (id 270) in project 1 (ESH10000633 system).

Update 2026-06-04 — empirical A/B confirmation via ESH10000589 GND-bridge relay

Method. Replaced the ad-hoc ground wire from the May 27 probe-check with a programmable bridge: the new ESH10000589 4-DPDT N-Top relay module (Host Accordion position N2, channel 0.12.ESH10000589._RELAY0) bridges FE AGND ↔ TA DMM_GND. Test rig now controls it from the Maestro orchestrator (tests/fixture-electronics-test.yaml → python_modules/fe_gnd_relay.py, prompt in tests/_prompt_gnd_relay.yaml). Operator prompted at start: gnd_relay_on=YES closes the bridge.

Ran the full FE orchestrator four times on the same DUT, same session: two runs with the relay OFF (1a, 1b — grounds isolated, baseline) and two runs with the relay ON (2a, 2b — grounds bridged). Within-config noise = |A−B| between the two repeats; mean effect = (mean ON) − (mean OFF).

Headline — J5 VREF (PT-PWR.10, the original symptom):

Δ is ~100× the within-config noise, confirming the May-27 root cause with a clean A/B design instead of a one-shot ad-hoc wire. With the bridge, J5-18 now sits within REF3425's ±1.25 mV initial accuracy without widening the window.

Cross-test confirmation of "GND-ON reduces HOST-side measurement noise": the user predicted this would generalise beyond J5 VREF to every measurement that returns through the TA→cables→Host path. Confirmed across the suite:

DUT-side VMON readings stay quiet in both configs (<3 mV) — they never depended on the cross-domain ground in the first place. The improvements all land on host-side / external-instrument paths, exactly as predicted.

Implication for the test rig. The ad-hoc wire from May 27 is now obsolete. The ESH10000589 relay gives the same effect on demand, programmable per-test. See the two decision entries filed on projectId 1 today: (1) GND-bridge ON by default in production tests; (2) split fe_Jx_gnd from fe_Jx_pwr — the new fe_Jx_gnd is the only sub-test where the relay must be OFF (otherwise the GND-pin continuity measurements always pass).

Reference dataset: 4 verification runs on this project's orchestrator, 2026-06-04 session.

As-built on DUT P0 (2026-06-04)

To exercise the new FE↔TA GND-bridge relay (ESH10000589 N-Top at Host Accordion N2, channel 0.12.ESH10000589._RELAY0), DUT P0 has been hand-reworked:

• One wire from FE J5 GND pin to a Phoenix header.
• One wire from TA GND to the same Phoenix header.
• Phoenix header plugs into the Host Accordion relay module so _RELAY0 can bridge / isolate the two grounds programmatically.

This rework is what made the 2026-06-04 4-run A/B experiment possible (see E-007 update — 5–54× noise reduction, J5 VREF Δ=−5.14 mV).

The wires are loose on the bench side of P0 — handle with care during transport / re-fitting. P0 is the only TA unit reworked this way; any other TA returning to this test rig needs the same rework before the GND-bridge relay can be exercised.

Update 2026-06-04 (afternoon) — wires moved to NC contacts

The two wires originally landed on the relay's NO (normally-open) contacts. They have been moved to the NC (normally-closed) contacts of _RELAY0 on the same ESH10000589 module.

Behaviour after the move:

Safer fail mode: any failure that leaves the relay un-commanded (power loss, missing module, dropped Accordion connection) lands grounds CONNECTED — the safe configuration for every FE sub-test except fe_Jx_gnd. The Maestro orchestrator only touches the relay around that one sub-test.

See projectId 1 / E-022 update for the test-rig software simplification this enabled (v1.0.246: dropped the operator prompt, the gnd_relay_on variable, and the setup / teardown relay-control steps).

Next-revision action (TA R≥2)

Add a dedicated GND-bridge header on the test adapter so this connection is built-in instead of hand-wired:

• One pin tied to TA AGND (the same node that the DMM_GND return decision E-008 will formalise).
• One pin routed to the FE J5 GND signal — pick the J5 GND pin that the test rig currently uses for the rework (J5 pin number TBD when laying out R2).
• Connector mates with a short cable to the Host Accordion N-Top relay module's NC contacts on _RELAY0 (preserves the safe-fail behaviour). The existing Phoenix-header convention used elsewhere in the rig is fine.

With the header in place, the GND-bridge relay is plug-and-play for every TA unit — no per-DUT rework, no loose wires.

Why this lives on the TA, not on FE

The relay itself is rig-side (Host Accordion N2). What the TA needs is just a clean external pickup point for the two grounds it owns (TA AGND + FE J5 GND via the IDC). The FE board's J5 connector already exposes the GND pins; routing them through the TA is what makes the rig-side relay possible without a custom cable harness on the FE side.

References

• projectId 14, E-007 — root cause + 2026-06-04 A/B dataset.
• projectId 14, E-008 — TA R1 dedicated DMM_GND return decision (related ground-architecture work; the new header should share the same TA AGND node).
• projectId 1, E-022 — decision: GND-bridge relay ON by default in production tests; update 2026-06-04 documents the NC-wiring simplification.
• projectId 1, E-023 — decision: split fe_Jx_gnd from fe_Jx_pwr (orchestrator now does isolate_grounds → fe_Jx_gnd → connect_grounds around the sub-test).

Patch on Sparrow Test Adapter (TA) S/N P0 — 2026-06-18

What: added a wire on the TA board joining test-adapter GND to the PSU-connector GND. Engineer-installed at bench.

Why: without this wire there's no galvanic path between PSU GND and DUT GND on the J4 differential bus. The PSU's GND was floating relative to the DUT GND through whatever resistance the chassis provided. Result: the differential bus self-biased and the ADC reads on the AIN bus came out as a noisy fraction of the commanded voltage (≈ V/2, varying step-to-step). With the GND wire installed, the ADC magnitudes now track the DMM within ≈ 0.1 % — the V/2 clustering reported in E-014 is gone.

Effect on the open issues:

• E-014 (N-Top ADC reads single-ended of one bus rail; values cluster at V/2): root cause was NOT the N-Top ADC architecture — it was the missing PSU↔DUT galvanic connection on the TA. With the GND wire installed, J4 ADC magnitudes are now correct across all 7 gains and all 6 voltage points (post-patch run a95f55da-9aa7-419c-ae9d-9c5b072e0291, 2026-06-18 11:14). E-014 will be closed once the residual sign-inversion concern (see below) is also resolved or filed separately.
• E-012 (J4 polarity relays don't flip): remains closed. The 5V mux drive + Y0/Y1 swap from v1.0.301 is unchanged and still correct — the DMM tracks PSU polarity perfectly in the post-patch run.

Residual concern (will file separately if it persists): in the same post-patch run, the ADC reads are still opposite sign of the DMM/PSU truth on every point (e.g. PSU=+5V → DMM=+5.0001V → ADC=−5.005V). Magnitude is right, sign is inverted. This produces CH*_GAIN_DEV_PCT ≈ −200% across all gains (slope observed = −1.0 vs ideal +1.0). Possible causes: (a) N-Top firmware ADC_CHn reports (AIN_N − AIN_P) not (AIN_P − AIN_N); (b) the TA wiring of AIN_P / AIN_N is swapped relative to the test-code assumption; (c) the Y0/Y1 → POS/NEG mapping needs re-verification under the new GND-connected condition. Will investigate after running v1.0.304 (8-channel restore) — if all 8 channels show the same sign inversion, it's a systemic wiring/firmware convention; if only some, it's per-channel.

Patch lives on: P0 only. Future TA revisions (R0 production builds) need this connection designed in — not as a patch. Worth a sister entry on TA-design tracking once we confirm R1 boards include the GND connection by default; if R0 production lacks it, this becomes a hardware ECN.

Reproducibility:

• Pre-patch comparison run: e8f41b11-bf67-4cad-8869-d7c184ca76df (2026-06-18 08:22, v1.0.302) — same DUT, same TA P0, no GND wire. ADC magnitudes 18-47% of bus, highly variable.
• Post-patch run: a95f55da-9aa7-419c-ae9d-9c5b072e0291 (2026-06-18 11:14, v1.0.302) — same setup with GND wire added. ADC magnitudes 100.1% of bus, consistent.