Accordion SO-DIMM precision ADC/DAC module — R2. 16-bit current set-point / 24-bit current readback. Sub-assembly of the Collimator LED Control Box (ESH10000672 R1).
Lightweight shell — full new_project workflow pending. Imported as a dependency of ESH10000672 R1.
Milestones
| Code | Title | Status | Target | Achieved | TC |
|---|---|---|---|---|---|
| MS-001 | Tape-out (PCB to JLC) | marker | 2026-07-03 | — | 0 / 0 |
| MS-002 | Bring-up | marker | 2026-08-28 | — | 0 / 0 |
Items (3)
| Code | Status | Severity | Kind | Title | Date |
|---|---|---|---|---|---|
| E-002 | open | warning | notice | ESH10000590 is an established SO-DIMM ADC/DAC product, newly imported into Trace | 2026-06-23 |
| E-003 | open | warning | notice | Open spec gaps on ESH10000590 — quantify before approval | 2026-06-23 |
| E-001 | open | info | decision | R2 change: ADC input divider network for 0–5 V full scale (R0 was 2.5 V) | 2026-06-23 |
Requirements
| Code | Status | Category | Title | Statement | Acceptance |
|---|---|---|---|---|---|
| REQ-001 | draft | Mechanical | Accordion SO-DIMM module form factor | The module shall be implemented as an Accordion SO-DIMM form-factor module, compatible with the Accordion M1 mainboard (ESH10000597) SO-DIMM interface (J9). | Module mates mechanically and electrically with the Accordion M1 SO-DIMM (J9) connector; pinout conforms to the SO-DIMM interface contract. |
| REQ-002 | draft | Performance | 24 ADC channels, 24-bit resolution | The module shall provide 24 ADC input channels, each with 24-bit resolution. | All 24 ADC channels enumerate and return 24-bit conversions. **TBD — achieved measurement accuracy (24-bit nominal ≠ accuracy; bounded by reference + divider network, see REQ-007).** |
| REQ-003 | draft | Performance | 24 DAC channels, 16-bit resolution | The module shall provide 24 DAC output channels, each with 16-bit resolution. | All 24 DAC channels enumerate and set output independently at 16-bit resolution. **TBD — achieved output accuracy.** |
| REQ-004 | draft | Performance | ADC input range 0–5 V full scale | Each ADC channel shall accept an input range of 0–5 V at full scale (achieved via the input divider network — see REQ-007). | Apply 0–5 V to an ADC channel input; conversion spans full scale without clipping. **TBD — accuracy/linearity over the range.** |
| REQ-005 | draft | Performance | DAC output range 0–5 V full scale | Each DAC channel shall produce an output range of 0–5 V at full scale. | Set DAC across code range; output spans 0–5 V. **TBD — accuracy/linearity over the range.** |
| REQ-006 | draft | Interface | All communication via I2C | All control and readback communication with the module (ADC reads, DAC writes, configuration) shall be over I2C. | All ADC and DAC channels are fully controllable/readable over I2C with no other control interface required. **TBD — I2C device addresses and bus map.** |
| REQ-007 | draft | Design | ADC input divider network for 5 V full scale (R2 change) | The ADC channels shall include an input divider network that scales a 0–5 V input to the ADC's native range, enabling 5 V full scale. This is the primary R2 change: the prior revision (R0) supported only 2.5 V full scale. | ADC channels read 0–5 V full scale (vs 2.5 V on R0). Divider present on all 24 ADC channels. **TBD — divider ratio, resistor tolerance, and input-loading/accuracy impact.** |
Test Cases
No test cases recorded.
Verification Records
No verification records.
Decisions
Decision
The primary R2 update to ESH10000590 is the addition of an input divider network on the ADC channels so they read 0–5 V full scale. The prior revision (R0) supported only 2.5 V full scale.
Why
The module must digitize 0–5 V signals from the stack — e.g. the INA2181A1 current-sense output on ESH10000584 (full scale 500 mΩ × 500 mA × 20 V/V = 5 V) and 0–5 V monitoring signals.
Consequence / to verify
- Divider ratio (likely ÷2) → the ADC sees half the input; confirm ratio.
- Resistor tolerance and input loading of the divider now contribute to ADC accuracy — fold into the measurement error budget.
- Voltage reference must support the intended full-scale; confirm.
Notices
ESH10000590 R2 (Accordion Precision ADC/DAC Module) is based on an established product with an R0 history, but was never previously tracked in Trace. REQ-001…007 (Draft) were reconstructed from the engineer's verbal description on 2026-06-23 — not yet validated against the authoritative schematic/BOM/design docs. Confirm against the real design before approving. Provides the precision ADC/DAC the rest of the stack relies on (e.g. set-point DAC + current-readback ADC for ESH10000584).
Values left unquantified in the drafted requirements — needed before approval / verification planning:
- ADC/DAC device part numbers and I2C address/bus map (REQ-002/003/006).
- Achieved accuracy — ADC (REQ-002/004) and DAC (REQ-003/005): 24-bit/16-bit are nominal resolutions, not accuracy. Bounded by reference + divider tolerance.
- REQ-007 divider — ratio (÷2?), resistor tolerance, input-loading/accuracy impact, and voltage-reference choice.
- 584↔590 analog interface — ESH10000584 (N-Top) sends/receives analog set & sense; ESH10000590 (SO-DIMM) holds the DAC/ADC. These connect through the M1 mainboard (ESH10000597) routing, not directly. Confirm the analog routing path and capture it as a formal interface once pinouts are known. (Mirror of decision E-003 on ESH10000584.)
Channel budget sanity: 584 needs ~8 set-point DAC + 8 current-readback ADC + 2 aux ADC — well within 590's 24 DAC / 24 ADC.
Design Rule Status
■ No violations ■ Warning ■ Error ■ Waived