TC-L-09 — DIO0 (IO5) passive state check

Probe the DIO0 line (SX1276 DIO0 → ESP32-C6 IO5) with a DMM while the device is powered and idle (no TX/RX in progress).

Expected: ~0 V (LOW). No interrupt is being generated at rest, so the pin should be low.

Note: a stuck HIGH on DIO0 would indicate a falsely-asserted interrupt. This would not cause mode transition failures, but could interfere with TX/RX completion handling once PLL issues are resolved.

Pass: DIO0 reads ~0 V at rest.