Sub-assembly verification provides full parametric characterization. Production test must be fast and focus on assembly integrity, bus connectivity, and end-to-end signal paths.

Trade-offs: Production test will be shorter than sub-assembly verification. Defects in individual PCBA performance (e.g. gain accuracy) are caught at sub-assembly level, not here. Follow-up: define clear boundary between sub-assembly vs production scope.

The two pull-up resistors R61/R67 are required for correct DRxD/DCTS pull behavior. R1 BOM omitted them as DNP — a defect uncovered during integration. R2 is a deliberate BOM correction, not a renumber. Mounting at the assembler (vs. internal rework on 60 boards) avoids rework throughput cost and produces clean R2 stock.

Trade-offs: 7 R1 pcs in Testing are write-offs for this build (can be reworked or kept as spares). Adds coordination overhead with the assembler to confirm R2 spec is applied on the 60-pc order before PCBA completion. Single-Manufacturing-rev discipline maintained (R2 sole Manufacturing rev as of 2026-05-15, R1 EOL).

Tolerance stack (confirmed 2026-05-25)

V_pullup derivation (AMS1117-ADJ + 100 Ω 1% × 2)

The 2.5 V rail is generated by AMS1117-ADJ (EGP10001062) with 100 Ω 1% top + 100 Ω 1% bottom on the ADJ pin. AMS1117 datasheet: V_REF = 1.225–1.275 V (±2%), I_ADJ = 50–120 µA.

V_out = V_REF × (1 + R_top/R_bot) + I_ADJ × R_top

I_ADJ contributes a ~+10 mV systematic positive offset (always pushes V_out up).

Divider math (Phase 3 + 4)

V_pin = V_pullup × R_load / (R_pullup + R_load)

YAML windows = worst-case corners rounded out 1 cV.

SPC evidence (14-sample run on SN 123)

Across 14 audio test executions on serial 123 (2026-05-22 to 2026-05-25):

Bias means cluster at 1.92 V (limit centre 1.905, mean +15 mV high) and phantom means cluster at 1.28 V (centre 1.26, mean +20 mV high) — consistent with V_pullup running ~2.51–2.56 V (+0.5 to +2.5% above nominal), well inside the +3.5% tolerance corner.

Cpk values 0.39–1.02 (industry rule of thumb wants Cpk ≥ 1.33) confirm the old limits were too tight — the measurement distribution did not have headroom for normal component variation. New limits give Cpk ≥ 2.0 on every measurement, providing process headroom.

V↔mA reconciliation with PT-SIG.04 spec (Q-AUDIO-001)

PT-SIG.04 spec: nominal MIC_BIAS supply current 2.273 mA (DMM-measured at 5 V into R_bias = 2.2 kΩ). Maestro test measures voltage at MIC_IN through the divider; the V-based YAML limits are equivalent. See Q-AUDIO-001 question 3.

Source documents

• Sparrow Hardware Datasheet v3, §6.7 (SIG-08 acceptance for R_phantom + R_bias)
• AMS1117 datasheet (V_REF, I_ADJ specs)
• PLEASE Q-AUDIO-001 (margin analysis discussion)
• Maestro execution UUIDs aaa9223e, 11052661, 064b135d, b3ae9c0e, 5fc58c14, ba45a309, e5b57494, c05ea5a7, f1157e66, ff399828, 5768f21a, 0176faa8 (12 runs on SN 123)

Trade-offs: ## Tradeoffs accepted

• Wider windows reduce defect-catching sensitivity. A DUT whose R_bias drifts to the high end of SIG-08's 2156–2264 Ω band combined with a fixture pullup at the low end of ±5% will now pass at ~2.00 V where it previously failed. Mitigation: SIG-08 still bounds the DUT bias resistor on its own; production-test SPC monitoring (get_measurement_statistics) will detect drift even within the relaxed limits.

• Limits derived from worst-case (not RSS) are conservative. Some sites prefer RSS (root-sum-square) limits assuming components are independent and Gaussian, which gives tighter windows. Worst-case was chosen because: (a) component count is small (3–4 contributors), (b) the test sample is limited (14 runs), and (c) production yield benefits more from preventing nuisance fails than from catching marginal DUTs that would pass on a different fixture.

• No fixture-side characterization captured yet. The AMS1117-ADJ output and the plug pullup R were not directly measured — limits derive from datasheet worst-case. If a per-fixture calibration is added later, limits can be tightened per fixture.

• Limits do not constrain DUT-side R_bias / R_phantom independently. A DUT whose components are at one extreme combined with a fixture at the other extreme can still pass the relaxed window. This is intentional — the test exists to catch assembly faults (missing parts, wrong polarity, broken solder) more than component-tolerance drift within spec.

Follow-up actions

1. Document derivation — done (this decision).
2. Update YAML limits — done (fe_J6_audio.yaml v1.0.216).
3. Add placeholder Limit Derivation sections to other test YAMLs — done (13 files, follow this pattern).
4. TODO: measure actual V_pullup on each test adapter and record per-fixture; consider tightening limits to ±fixture-specific corner instead of ±worst-case-IC corner.
5. TODO: when DUT batch yield analysis is done in Phase 11, cross-check whether tightening back toward the previous 1.86–1.95 V is feasible given the production population's bias-resistor distribution.

Test Adapter divider topology (confirmed 2026-05-25)

Per Sparrow_TA_R0 schematic (ESH10000654 R0, sourceRef: ESH10000654/R0/02_Implementation/DesignFiles/Sparrow_TA_R0.pdf):

Both divider pairs use 1% tolerance resistors (EGP10000121 = 100K, EGP10000097 = 10K).

Tolerance stack

5V_DIV corner math

V_mid = V_5V × R_bot / (R_top + R_bot)

YAML window = 2.33–2.67 V (rounded outward).

12V_DIV corner math

V_mid = V_12V × R_bot / (R_top + R_bot)

YAML window = 1.00–1.18 V (rounded outward).

GND corner math

Expected V = 0 V (connector GND tied to system GND through ribbon-cable return).

Contributing terms:

• GND return IR drop: PWR-25 caps total rail current at 1.5 A through the PTC. PCB+ribbon-cable GND impedance ≤ 50 mΩ → worst-case 75 mV drop.
• MPIO offset: ±8 mV (SIG-01).

Worst-case total ≈ 75 + 8 = 83 mV.

Production-safe YAML window = 0.00–0.10 V — leaves a small margin above the physical worst case while still catching any gross GND-integrity fault (broken connector tab, oxidation, unmated pin, missing ribbon-cable return).

Source documents

• Sparrow Hardware Datasheet v3 §6.1–6.2 — common rail specs (PWR-01, PWR-02, PWR-25)
• Sparrow_TA_R0 schematic — divider topology and resistor BOM
• PLEASE PWR-01, PWR-02, PWR-25, SIG-01 — sourceRef = ESH10000633/R1/01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf

Trade-offs: ## Tradeoffs accepted

• 5V_DIV window widened from ±100 mV to ±170 mV. Previous window (2.40–2.60 V) was tighter than the rail-spec + resistor-tolerance + MPIO-accuracy corner could deliver — at 4.75 V rail + worst resistor corners + MPIO gain/offset corner, a healthy unit could land at 2.336 V and fail. The widened window matches the design's actual capability without losing detection of real rail failures (a rail down to ~4.0 V would still read ~2.0 V and fail the low limit).

• 12V_DIV window tightened on the high side (1.4 V → 1.18 V). The previous high limit (1.40 V) accepted readings 22% above the worst-case corner (1.166 V raw) — a placeholder, not a derived limit. New high limit catches any actual rail overshoot (>12.6 V would be visible). Low limit (1.00 V) is unchanged; corner is 1.007 V so a healthy unit still passes with 7 mV margin.

• GND window tightened from 200 mV to 100 mV. Physical worst case is ~83 mV (1.5 A through 50 mΩ + MPIO offset). 100 mV leaves a small margin. If a future fixture has worse GND cabling (>50 mΩ), the test could nuisance-fail — mitigated by ensuring the test adapter and ribbon harness meet the PCB-impedance assumption.

• Limits derived from worst-case (not RSS) are conservative. Some sites prefer RSS (root-sum-square) limits assuming components are independent and Gaussian; that would give windows ~15% tighter. Worst-case was chosen because (a) component count is small (3 contributors: V_rail, R_top, R_bot), (b) the test runs against a population of physical units where component skew can be systematic per-fixture (e.g. one PCB lot may have all R's biased one way), and (c) production yield benefits more from preventing nuisance fails than from catching marginal DUTs that would pass on a different fixture.

• No per-fixture calibration. Limits derive from datasheet worst-case. If per-fixture characterisation of the actual V_5V / V_12V rails and divider mid-points is added later, limits can be tightened per fixture.

• GND limits assume realistic test-time current draw. The 75 mV bound uses PWR-25's 1.5 A PTC limit; actual current at the moment the GND pins are read is typically <0.5 A (most loads off), so the 100 mV window has comfortable real-world headroom.

Follow-up actions

1. Update YAML limits — done (fe_Jx_pwr.yaml v1.0.0).
2. Document derivation — done (this decision).
3. TODO: Capture the Test Adapter BOM into PLEASE via please_component_create so the 1% resistor tolerance assumption is structured, not just a comment in the YAML.
4. TODO: After ≥10 production runs, pull SPC stats and verify Cpk ≥ 1.33 on all 28 measurements. If margins are excessive, consider tightening (especially GND).
5. TODO: Cross-reference D.04 from PLEASE test cases PT-PWR.01..02 (if/when those exist) once a coverage matrix is built for fe_Jx_pwr's pt_codes.

Tolerance stack

Worst-case math (representative samples — same pattern applies to every rail)

1V8_EXT VMON (direct → ADS7828)

V_mon = V_rail × ADC_gain ± ADC_offset

YAML window → 1.746–1.834 V.

3V3_EXT VMON (1 K + 1 K → ADS7828)

V_mon_reported = V_adc_read / nominal_ratio where V_adc_read = V_rail × actual_ratio × ADC_gain ± ADC_offset

Actual ratio with ±1 % R's: low = 990 / (1010+990) = 0.495; high = 1010 / (990+1010) = 0.505. Nominal = 0.500.

YAML window → 3.172–3.431 V.

12V_EXT VMON (4K3 + 1 K → ADS7828)

Actual ratio: low = 990/(4343+990) = 0.18564; high = 1010/(4257+1010) = 0.19177. Nominal = 1/5.3 = 0.18868.

YAML window → 11.32–12.70 V.

12V_EXT HOST_V_DIV (TA 1 K + 124 Ω → MPIO)

Actual ratio: low = 122.76/(1010+122.76) = 0.10838; high = 125.24/(990+125.24) = 0.11230. Nominal = 124/1124 = 0.11032.

YAML window → 1.245–1.405 V (rounded outward).

VIO @ 2.5 V VMON (direct → AD5593R) — representative for direct-to-AD5593R group

YAML window → 2.443–2.558 V.

VADJ @ 2.5 V VMON (1 K + 1 K → AD5593R) — representative for divided-to-AD5593R group

YAML window → 2.413–2.588 V.

MPIO chain (HOST_V) — representative VIO @ 2.5 V

YAML window → 2.445–2.556 V.

Source documents

• Sparrow Hardware Datasheet v3 §6.2 — external rail specs (PWR-03..07)
• Sparrow Hardware Datasheet v3 §6.11 — VMEAS / IMEAS chain accuracy (PWR-10, PWR-11)
• Sparrow Fixture Electronics PCBA ESH10000540 R3 — FE-side ADC + divider chain (ADS7828EB EGP10000946, AD5593R EGP10000890)
• Sparrow Test Adapter ESH10000654 R0 — TA-side 12V divider (R51 = 1 K, R52 = 124 Ω)
• PLEASE SIG-01 — host MPIO accuracy

Trade-offs: ## Tradeoffs accepted

• Chain-specific windows (not unified). Each rail has separate VMON and HOST_V windows derived from its own measurement chain. For most rails the two windows differ noticeably (e.g. 3V3_EXT: VMON 3.172–3.431 V vs HOST_V 3.212–3.388 V — HOST_V tighter because MPIO is more accurate than the FE ADC chain). For VIO setpoints the windows happen to coincide because AD5593R and MPIO have similar accuracy budgets. Maintenance cost: ~28 distinct limit pairs in the YAML, but each window correctly reflects what its chain can produce — better cross-check and better Cpk in production.

• Asymmetric rail-spec handling kept literal. PWR-04 (3.23–3.37 V) and PWR-05 (1.76–1.82 V) are asymmetric around their nominal. The new windows preserve that asymmetry rather than smoothing to ±N%, so a unit at the spec edge can still pass.

• VMON windows for 1V8_EXT, VIO @ 1V5, VIO @ 1V8, VIO @ 2V5, VIO @ 3V3 are TIGHTER than the previous ±3 % placeholder. Previous windows were not derived; new windows reflect the actual chain capability. A unit measuring outside the new (tighter) window now indicates a real fault (drift, calibration loss, or rail issue) rather than a placeholder margin.

• VMON windows for 3V3, 12V, VADJ (all setpoints) are SLIGHTLY WIDER than the previous ±3 %. The earlier ±3 % could nuisance-fail a unit at the spec edge whose ADC chain corner happened to push the reading outside ±3 %. New windows give correct headroom without losing real fault detection (a 3V3 rail at 3.10 V would still fail the new 3.172 V floor).

• ADC accuracy estimated at ±0.5 % gain + ±5 mV offset (conservative). ADS7828EB and AD5593R both have:

  • Initial typical: ±0.05 % gain, ±0.1–0.2 % Vref → ~ ±0.2 % gain total
  • Vref temp drift: ±10 mV (~ ±0.4 %)
  • Long-term aging: ~ ±0.05 %/year × 5 years = ±0.25 %
  • INL + offset: ~ ±2 LSB ≈ ±1.2 mV at 2.5 V Vref
  • Combined: ~ ±0.5 % + ±5 mV is conservative for steady-state production with environmental swing. Tighter limits possible after per-fixture calibration.

• No per-fixture calibration captured. All limits derive from datasheet worst-case for both the FE and TA boards. A future calibration pass could tighten the windows per fixture (especially for the 12V_EXT_DIV which has a 1 K + 124 Ω TA divider that varies fixture-to-fixture).

• PRE/POST/IMON limits unchanged. These were not derived from spec in the first place — they're practical thresholds set during early bring-up. Will revisit in a follow-up if production data shows nuisance-fails or systematic drift.

• 12V_EXT_DIV YAML comment updated. Previous comment said "12 / 9.09 = 1.32 V nominal, ±5 %"; new comment reflects the actual TA topology (R51 = 1 K + R52 = 124 Ω → 1.323 V) and the corner-derived window (1.245–1.405 V).

Follow-up actions

1. Update YAML limits — done (fe_J9_pwr.yaml v1.0.0, 28 ON-state windows + header rewritten).
2. Document derivation — done (this decision).
3. TODO: Capture the FE-side ADC chain (ADS7828EB + dividers) into PLEASE as please_component_create entries with sourceRef pointing at the Sparrow FE schematic, so the ±1 % R / ±0.5 % ADC assumptions are structured rather than free-text in this decision.
4. TODO: Capture the TA 12V_EXT_DIV divider (R51 = 1 K, R52 = 124 Ω) into PLEASE — same as D.04 follow-up #3.
5. TODO: After ≥10 production runs through fe_J9_pwr, pull SPC stats on every ON_VMON and ON_HOST_V measurement; verify Cpk ≥ 1.33. Identify any measurement where the rail is consistently biased to one side of the window — likely indicates a systematic divider or ADC offset that could be calibrated out.
6. TODO: Cross-reference D.05 from any PLEASE test cases that get created for pt_code tags in fe_J9_pwr.yaml once a coverage matrix is built.

Topology (FE side, Sparrow Fixture Electronics PCBA ESH10000540 R3, schematic page 6)

Transceiver: MAX491ESD+T (U24, EGP10001593) — full-duplex RS-485/RS-422, VCC = 5 V, not slew-rate-limited, datasheet rate to 2.5 Mbps. Pinout per Maxim datasheet: pin 4 DE (active high), pin 3 R̅E̅ (active low, tied to RS485_EN logic), pin 9 Y (driver+) → RS485_TX+, pin 10 Z (driver-) → RS485_TX-, pin 11 B (receiver-) → RS485_RX-, pin 12 A (receiver+) → RS485_RX+.

Loopback path: Sparrow Test Adapter (ESH10000654 R0) shorts RS485_TX+ ↔ RS485_RX+ and RS485_TX- ↔ RS485_RX- on the J9 IDC connector. R64 = 120 Ω across RS485_RX+ ↔ RS485_RX- on the FE acts as the bus termination/load when looped back to TX. Effective driver load = 120 Ω.

No FE-side fail-safe bias network. Verified by netlist inspection: no Vcc → Rb → A / B → Rb → GND resistor pair anywhere near U24. When EN=false, the line floats via the diff-amp resistor network (168 K total) to the ADC inputs (HiZ).

VMEAS chain (per schematic + netlist trace):

RS485_TX+ ── R208 (140K) ── A ── R240 (14K) ── B ── R207 (14K) ── RS485_TX-
                            │                       │
                          R245 (120Ω LP)         R246 (120Ω LP)
                            │                       │
                          U40 CH0                 U40 CH1        (ADS7828EB, single-ended to GND)

RX side mirrors TX: R206 (140K), R239 (14K), R205 (14K), R247/R248 (120 Ω LP), U40 CH2/CH3.

All chain resistors are 1 % tolerance (EGP10001834 for 14K, EGP10001584 for 140K, EGP10000052 for 120Ω). ADC is ADS7828EB (EGP10000946), same part as on the rail VMEAS chains.

Schematic annotation (page 6, near the ADC block): Vout = (V+ − V-) × R2 / (R1 + R2 + R3) = (V+ − V-) / 12

DC analysis (ADC inputs HiZ):

i = (V_TX+ − V_TX-) / (R208 + R240 + R207) = (V_TX+ − V_TX-) / 168K
V_node_A = V_TX+ × 28/168 + V_TX- × 140/168
V_node_B = V_TX+ × 14/168 + V_TX- × 154/168
V_node_A − V_node_B = (V_TX+ − V_TX-) × 14/168 = (V_TX+ − V_TX-) / 12   ✓

So V_diff_reported = (V_A_adc − V_B_adc) × 12 = V_OD (line-level differential).

Tolerance stack

For the EN=true window we use the COM-08 published chain accuracy (which envelopes the underlying resistor + ADC contributions and is the spec the FE was designed against).

Corner math — EN=true

V_reported = V_OD × (1 ± 0.016) ± 0.006 V

YAML window (rounded outward to 0.1 V) → 2.0 – 3.5 V.

Note: the upper bound was deliberately rounded inward to 3.5 V (vs. 4.07 V worst-high). Reason: a V_OD reading > 3.5 V at 120 Ω load on a MAX491 powered from 5 V is unusual — it suggests near-no-load conditions (broken R64 termination on RX side, broken loopback short on TA, or VMEAS chain calibration drift). Catching that is worth the slight reduction from the spec ceiling. If production data shows occasional readings between 3.5 V and 4.0 V on healthy units, widen the upper bound.

Corner math — EN=false

Driver tri-state. No FE-side fail-safe bias network (confirmed by schematic inspection). Line floats via the 168 K diff-amp network to ADC inputs (HiZ).

YAML window → 0.00 – 0.05 V (allows ~5× the worst-case RSS for safety margin while catching any genuine line stuck-state or driver short).

The previous 0.0–0.1 V is wider than needed; tightening to 0.05 V catches a stuck driver (V_OD = 0.05–0.1 V) that the looser window misses.

Source documents

• MAX491ESD+T (EGP10001593) — Maxim Integrated MAX491 datasheet (full-duplex RS-485/RS-422 transceiver, VCC = 5 V, V_OD @ 54Ω spec 1.5 V min / 2.5 V typ)
• ADS7828EB (EGP10000946) — TI ADS7828 datasheet (12-bit ADC, ±0.5 % gain, ±2 LSB offset at 2.5 V Vref)
• Sparrow Fixture Electronics PCBA ESH10000540 R3 — schematic page 6 ("Fixed Load. UART-RS485.") and netlist (NetList_Sparrow_FE_R3.qcv)
• Sparrow Test Adapter ESH10000654 R0 — TX↔RX loopback short
• PLEASE COM-05, COM-08, COM-09 — RS485 functional requirements + VMEAS chain accuracy (gain ±1.6 %, offset ±6 mV)

Trade-offs: ## Tradeoffs accepted

• EN=true window widened from 2.5–3.0 V to 2.0–3.5 V. Previous 0.5 V window was tighter than MAX491 V_OD variation over -40°C to +85°C at the 120 Ω loopback load — a unit at V_OD = 2.3 V (well within MAX491 spec) would nuisance-fail the 2.5 V floor; a unit at V_OD = 3.2 V would nuisance-fail the 3.0 V ceiling. New 2.0–3.5 V window catches a degraded driver (V_OD < 2.0 V indicates driver impedance ≫ datasheet typical) while tolerating in-spec variation.

• EN=true window tighter than COM-08 spec-floor (1.5–5.0 V). Pure spec-floor would also be valid but would only catch "VDIFF outside the requirement" — i.e., catastrophic failure. The chosen 2.0–3.5 V window catches degradation that's still technically in-spec but indicates trouble. Acceptable tradeoff: spec-compliant units are not penalized (V_OD < 2.0 V at 120 Ω load is below MAX491 typical even at temperature extremes), but degraded units are flagged before they cause field problems.

• EN=true upper bound rounded inward (3.5 V vs. corner 4.07 V). A reading > 3.5 V at 120 Ω load is unusual for a healthy unit — V_OD > 4.0 V would imply near-no-load conditions (broken termination R64, broken TA loopback short, or VMEAS calibration drift). Flagging it catches real test-rig integrity faults. Risk: a healthy unit at the upper temp/process corner could land at 3.55 V and nuisance-fail. Will revisit if production data shows this.

• EN=false window tightened from 0.0–0.1 V to 0.00–0.05 V. Previous window allowed up to 100 mV residual — physically the line should be very close to 0 V (no driver, no fail-safe bias). 50 mV ceiling catches a stuck or partially-driven output while tolerating chain offset (±6 mV) and worst-case residual leakage. If production shows nuisance-fails, widen back to 0.1 V or implement a signed window (-0.03 to +0.03 V).

• Low-bound at 0.00 V not negative. Assumes the software reports |V_diff| (absolute value) or clamps negative readings. If the actual report is signed and the line drifts slightly negative (V_TX- > V_TX+ from imbalance), this window would fail. If empirical data shows negative readings, change to e.g. -0.03 to +0.05 V.

• No FE-side fail-safe bias confirmed by schematic + netlist inspection. This is unusual for an RS-485 design (most boards add Vcc → 680 Ω → A and B → 680 Ω → GND for fail-safe MARK in tri-state). Sparrow FE relies on the loopback test running in EN=true mode for receiver fail-safe validation — but in a non-loopback deployment, the line might not assert MARK reliably when no driver is active. Flagged as a possible future design improvement, not a test issue. Documented in COM-09 acceptance (which mentions "receiver fail-safe bias" — verify the MAX491's internal fail-safe receiver works correctly at the floating bus voltages we see in EN=false).

• Loopback string-mode results (PASS / true) untouched. These are pass/fail outcomes from the loopback runner — not derived analog windows. They catch any byte corruption at any baud rate; correct as-is.

• Conservative outward rounding on EN=true low (2.0 V vs. corner 1.962 V). Round outward to give 38 mV margin. Catches the same failure modes as 1.96 V but gives more room for chain variation.

Follow-up actions

1. Update YAML limits — done (fe_J9_rs485.yaml v1.0.0, 4 line-level windows updated, derivation header added).
2. Document derivation — done (this decision).
3. TODO: After ≥10 production runs through fe_J9_rs485, pull SPC stats on RS485_LINE_EN_TX_VMEAS and RS485_LINE_EN_RX_VMEAS. Confirm:
   • All units land within 2.0–3.5 V (otherwise widen)
   • Distribution is symmetric / Gaussian around ~3.0 V (otherwise investigate)
   • No systematic bias TX vs RX (otherwise investigate VMEAS chain calibration)
4. TODO: Capture the MAX491ESD+T (EGP10001593) into PLEASE via please_component_create with V_OD spec, so the assumption is structured rather than free-text here.
5. TODO: Capture the FE diff-amp resistor chain (R208/R207/R240/R245/R246 and RX mirror) into PLEASE — same as D.04/D.05 follow-up #3.
6. TODO: Cross-reference D.06 from any PLEASE test case (PT-COM-*) that maps to a pt_code tag in fe_J9_rs485.yaml once a coverage matrix is built.
7. TODO (design-level note for next revision): Consider adding an external RS-485 fail-safe bias network on the FE (Vcc → 680 Ω → RS485_RX+; RS485_RX- → 680 Ω → GND). The MAX491 has internal fail-safe but it relies on a specific input voltage. With no external bias, the floating line in EN=false depends on leakage and the diff-amp network. Not a test issue today (test is loopback) but matters in production deployment.

Chain topology — Step 2 (RELAY fabric)

The J7 fabric is not a simple "10 kΩ to 2.5 V on the TA, MPIO/relay drivers on the FE". It passes through three boards and the components on each affect both the idle voltage and the pulled-low voltage.

Per-J7-pin chain (from TA back to FE)

TA pullup network (patches #1 + #2)
    10 kΩ ±5 %  →  2.5 V (TA AMS1117, per D.03: 2.425–2.588 V)
              │
           J7 pin (IDC connector on N-Top, EGP10001499)
              │
          ┌───┴────────────────────────────────────────────────────┐
          │ N-Top board (ESH10000634 R3)                            │
          │                                                         │
          │   For FE_MPIO_8..11 pins (J7-4, 6, 8, 10):              │
          │     ──→ ADG4612 switch (R_DS_on ~1 Ω, always ON via     │
          │         R12/R13 1 kΩ pullup to 5 V on U2/U3 IN)         │
          │     ──→ 39 Ω 1 % series R (R4/R5/R8/R9)                 │
          │     ──→ TVS KGSOT05C to GND (D31, D32; leakage ~nA)     │
          │     ──→ LSHM J3 pin (DATA1-56..59)                      │
          │                                                         │
          │   For RELAY1..4 pins (J7-12, 14, 16, 18):               │
          │     ──→ 220 Ω || 220 Ω = 110 Ω (R20||R21 etc.)          │
          │     ──→ G20N06D52 MOSFET drain (R_DS_on ~mΩ, negligible)│
          │     ──→ Source → GND                                    │
          │     ──→ Gate driven by FE USR_GPIO1..4 via 3K3 pulldown │
          │         (R31..R34, fail-safe gate-low when FE HiZ)      │
          │     ──→ TVS VGSOT24C on drain (D87, D88; ESD/flyback)   │
          └─────────────────────────────────────────────────────────┘
              │
       LSHM J3 pin (data line between FE and N-Top)
              │
          ┌───┴────────────────────────────────────────────────────┐
          │ FE board (ESH10000540 R3)                              │
          │   For FE_MPIO_8..11 (J3-7, 8, 11, 12):                 │
          │     ──→ 1 MΩ pulldown to GND (R171..R174, per SIG-12)  │
          │     ──→ AD5593R U6 (DAC/ADC channel, IO0..IO3)         │
          │                                                         │
          │   For USR_GPIO1..4 (J3-13..16) — the "RELAY drivers":  │
          │     ──→ from PCA9506 I/O expander U7 (open-drain        │
          │         outputs to N-Top's MOSFET gates)                │
          └─────────────────────────────────────────────────────────┘

Note: the test's "RELAY1..4" signals are not controlled by FE-side 2N7002 MOSFETs — they're driven by USR_GPIO1..4 (FE I/O expander) through the LSHM, which then drive the G20N06D52 MOSFETs on the N-Top board (Q1, Q2). The MOSFETs' drains pull the J7 fabric rail toward GND through the 110 Ω current-limit network.

Chain topology — Step 1 (FE_MPIO 0..7 loopback)

Same as Step 2 for the FE_MPIO routing (39 Ω + ADG4612 + TVS through N-Top) except:

• No TA pullup (TA shorts paired channels directly: J7-4↔J7-8, etc.)
• No RELAY drivers in play
• DAC drives one channel, ADC reads the other via the loopback short

At HiZ ADC input current, the 39 Ω + ADG4612 elements introduce sub-mV drops at all test voltages (4 V, 0.5 V, 0 V). So Step 1 windows are dominated by the AD5593R DAC + ADC accuracy, as originally derived.

Tolerance stack — Step 2

Step 2 corner math — corrected

Rail at pullup (idle / pulled-high)

Each rail has two MPIO branches, each ending in 1 MΩ to GND on the FE → 500 kΩ parallel pulldown loads the 10 kΩ TA pullup. The N-Top series chain (39 Ω + 1 Ω ADG4612) is in series with each pulldown but adds negligible drop at the 5 µA idle current per branch.

V_rail = V_pullup × R_pulldown_par / (R_pulldown_par + R_pullup) − I_MOSFET_leak × R_pullup

YAML window → 2.34 – 2.56 V (rounded outward to 5 mV).

The nominal is 2.451 V, not 2.5 V — the FE-side 1 MΩ pulldowns load the rail by ~50 mV. Important for production SPC analysis: the distribution should centre around 2.45 V, not 2.5 V. Anyone interpreting "rail at pullup = 2.5 V" needs to expect 2.45 V instead.

Rail pulled-low (driver active)

The N-Top inserts deliberate current-limiting in series with every driver path. The driver doesn't pull the rail all the way to GND — it pulls it down through a divider against the 10 kΩ pullup.

Worst-case readings:

• Worst-low: 0 V (driver can't go negative) − 8 mV (ADC offset) = −0.008 V
• Worst-high: 30 mV (relay-side high corner) + 8 mV (ADC offset) = +0.038 V

YAML window → −0.01 to +0.05 V (rounded outward, slight margin on high side).

The previous symmetric ±0.05 V window allowed up to −50 mV on the low side, which can't physically happen — only the ADC offset can produce negative readings. Tightening the low bound to −0.01 V catches a stuck-high reading earlier without losing any real-fault sensitivity.

Step 1 corner math — unchanged

DAC+ADC compounded chain, same as original D.07: 4.0 V → 3.96–4.04 V; 0.5 V → 0.48–0.52 V. The N-Top series chain (39 Ω + 1 Ω ADG4612 each direction, ~80 Ω round-trip) doesn't introduce gain/offset error at HiZ ADC current, so the original AD5593R chain math holds.

Source documents

• Sparrow FE PCBA ESH10000540 R3 — schematic page 4 (U5/U6 AD5593R + R171..R174 pulldowns), schematic page 3 (U7 PCA9506BS I/O expander → USR_GPIO1..4 driving J3-13..16), schematic page 9 (FE J3 LSHM connector)
• Sparrow IDC N-Top PCBA ESH10000634 R3 — schematic + netlist NetList_Sparrow_FE_N-Top_R3.qcv (U2/U3/U4 ADG4612, Q1/Q2 G20N06D52, R3..R17 39 Ω, R20..R30 220 Ω, R31..R34 3K3, R12/R13/R19 1 kΩ, D31/D32 KGSOT05C, D87/D88 VGSOT24C)
• Sparrow Test Adapter ESH10000654 R0 — patches #1 + #2 (DUT-01 / S/N P0): 10 kΩ ±5 % pullup to 2.5 V on rail A + B (notices 22 + 23)
• PLEASE D.03 — TA AMS1117 V_pullup tolerance (+3.5 % / −3.0 %)
• PLEASE SIG-02 — FE_MPIO chain accuracy (±0.3 % / ±8 mV per direction)
• PLEASE SIG-12 — MPIO pulldown spec (1 MΩ to GND)
• PLEASE Q-TA-01 — open: R48 function on TA
• AD5593R datasheet (EGP10000890), ADG4612 datasheet (EGP10001881), G20N06D52 datasheet (EGP10001048)

Trade-offs: ## Tradeoffs accepted

Step 1 — loopback windows widened (unchanged from initial D.07)

• Drive 4 V / 0.5 V windows widened from ±0.02 / ±0.01 V to ±0.04 / ±0.02 V. Previous windows assumed a single-direction chain accuracy (DAC OR ADC, not both). Loopback compounds both, so the corner is ±0.04 V at 4 V and ±0.02 V at 0.5 V. New windows match the chain corner without losing fault sensitivity (open driver, broken loopback short, stuck DAC code all still caught).

• INIT, crosstalk, kept. INIT at ±0.01 V matches the SIG-02 offset bound. Crosstalk at ±0.1 V is a practical capacitive-coupling allowance during the drive transient (DC corner is sub-mV).

Step 2 — rail-at-pullup window corrected (this revision)

• Window shifted DOWN from 2.40–2.62 V to 2.34–2.56 V (centred on 2.45 V, not 2.5 V). Earlier derivation in D.07 missed the FE-side 1 MΩ pulldowns on each FE_MPIO line. With 2 MPIO lines tied to each rail via TA patches #1 + #2, the parallel pulldown (500 kΩ) loads the 10 kΩ TA pullup and drops V_rail by ~50 mV at idle. The 2.40 V floor in the earlier version would nuisance-fail at worst-corner (cold rail + leakage at 85 °C → 2.339 V at the ADC). The corrected window accommodates the real corner and centres on the physically-expected 2.45 V nominal.

• Tighter than the previous placeholder ±0.2 V (2.3–2.7 V). New 2.34–2.56 V window catches small drift (AMS1117 reference shift, ADC calibration loss, leaky driver) that the placeholder window missed.

• Production SPC implication: the distribution centres on 2.45 V, not 2.5 V. Anyone reading the YAML number 2.5 V nominal should expect actual readings at ~2.45 V; only failures below 2.34 V or above 2.56 V are real issues. Cpk analysis should use 2.45 V as the target.

Step 2 — pulled-low window tightened asymmetric (this revision)

• Tightened from −0.05/+0.05 V to −0.01/+0.05 V (asymmetric). The previous symmetric ±0.05 V allowed up to −50 mV on the low side, which is physically impossible (no driver source drives negative; only the ADC offset can produce a negative reading, bounded by ±8 mV per SIG-02). Tightening to −0.01 V (with 2 mV margin past the ADC offset) catches a stuck-high reading earlier.

• High bound 0.05 V unchanged. Worst-case is 30 mV (relay-side V_rail = 2.5 V × 110 / 10110) + 8 mV ADC offset = 38 mV. 50 mV ceiling leaves 12 mV margin for component drift.

• Two distinct expected V_rail values in pulled-low state. MPIO-driven readings will cluster at ~10 mV; relay-driven readings at ~27 mV. Both pass the −0.01 to +0.05 V window. Production SPC implication: a histogram of pulled-low readings should show a bimodal distribution (10 mV peak for MPIO drives, 27 mV peak for relay drives). A unimodal distribution at 10 mV across scenarios where relays SHOULD fire would indicate the MOSFET driver isn't being engaged correctly.

Test depends on multiple boards' patches/topology

• TA patches #1 + #2 required for the Step 2 fabric to exist (see DUT-01 notice 22, 23). On a clean ESH10000654 R0 (no patches), Step 2 readings would float.

• N-Top board ESH10000634 R3 is on the path with active circuitry. Steps 1 and 2 both rely on the ADG4612 switches being ON (kept by R12/R13/R19 pullup to 5 V). If 5 V on the N-Top is missing or degraded, the switches go OFF and the whole test loses signal continuity. This is a single point of failure not currently tested in isolation.

• FE I/O expander U7 must work for RELAY1..4 to be drivable. USR_GPIO1..4 are open-drain outputs from U7 (PCA9506BS) at I²C address 0x20. Loss of the I/O expander → no relay drive → fabric stuck at pullup. This is checked indirectly (any I²C scan would catch a dead U7), but a dedicated USR_GPIO drive-and-verify step would be more direct.

Stack assumptions documented for future verification

• Worst-case stack (not RSS) used. RSS would give 15–30 % tighter windows but assumes independence of all error sources, which we can't guarantee (resistor lots can skew systematically; thermal correlation across nearby components).

• MOSFET drain leakage modelled at 2 µA per rail @ 85 °C. Conservative — could be lower (sub-µA total) at room temp. Will revisit if production data shows headroom on the high side of the pullup window.

• No per-board calibration. All limits derive from datasheet worst-case for FE U5/U6 (AD5593R), N-Top U2/U3/U4 (ADG4612), N-Top Q1/Q2 (G20N06D52), and TA U3 (AMS1117). Per-fixture calibration could tighten windows substantially, especially the pulled-low side where the TA-specific 10 kΩ patch resistor dominates.

Step 1 derivation re-verified through N-Top chain

• 39 Ω + ADG4612 on every FE_MPIO line confirmed for FE_MPIO_0..7 (Step 1) as well as 8..11 (Step 2). U4 ADG4612 covers FE_MPIO_4..7, U3 covers MPIO_2/3/10/11, U2 covers MPIO_8/9. Loopback test paths therefore each have ~80 Ω round-trip series resistance — negligible at HiZ ADC current. The original AD5593R chain math (D.07 Step 1) is unaffected.

Follow-up actions

1. Update YAML limits — done (44 of 100 windows changed; 56 kept).
2. Document derivation (corrected for N-Top chain + FE pulldown loading) — done (this decision).
3. Capture N-Top components in PLEASE (ADG4612, G20N06D52, R-chain, TVS diodes) — already in PLEASE Brain (projectId 7) from earlier _merge_mes_bom.py ingestion. Same for FE 1 MΩ pulldowns (projectId 5). Enriching descriptions/properties for the relevant components is a separate cleanup task.
4. TODO (open): Answer Q-TA-01 — R48 function. Independent of D.07 but blocks "clean Sparrow TA R0 acceptance criteria".
5. TODO: After ≥10 production runs through fe_J7_mpio_relay, pull SPC stats:
   • Pullup readings should cluster around 2.45 V (NOT 2.5 V). Cpk ≥ 1.33 within 2.34–2.56 V.
   • Pulled-low readings should show bimodal distribution at ~10 mV (MPIO-driven) and ~27 mV (relay-driven). Confirm both clusters within 0–50 mV.
   • Drive 4 V Cpk ≥ 1.33 within 3.96–4.04 V.
6. TODO: Verify the sample timing in fe_J7_mpio_relay.py (re crosstalk window decision).
7. TODO: When the next-rev TA (ESH10000654 R1) lands with the relay-readback fabric in-schematic (per notice 25), update this YAML's header to remove the "depends on patches" warning.
8. TODO: Add a dedicated test step that exercises USR_GPIO1..4 directly (drive HIGH and verify the N-Top MOSFET drains pull low). Currently this is checked indirectly via the fabric test.
9. TODO: Cross-reference D.07 from any PLEASE test case (PT-SIG-*) that maps to a pt_code tag in fe_J7_mpio_relay.yaml.

Change history

• 2026-05-25 (D.07 initial): Derived windows assuming TA-only pullup chain (missed N-Top series elements + FE pulldown loading). Step 2 pullup window was 2.40–2.62 V; pulled-low ±0.05 V.
• 2026-05-26 (this revision): Corrected after tracing FE → LSHM → N-Top → IDC J7 chain via Sparrow_FE_N-Top_R3 schematic + netlist. Identified ADG4612 switches, 39 Ω series, 220 Ω/MOSFET relay-driver chain, and the FE-side 1 MΩ pulldowns. Step 2 pullup window shifted to 2.34–2.56 V (centred on 2.45 V); pulled-low tightened asymmetric to −0.01/+0.05 V.

Chain topology

The fixed-load test exercises 4 NMOS switches on the FE that pull each J5 channel toward GND through a 2.2 kΩ FE-side resistor. The TA pullup (2.2 kΩ to 2.5 V) sets the open-state voltage; the FE VMEAS divider (100 K + 100 K) reads the J5 pin through a passive ÷2 attenuator. Software multiplies the ADC reading by 2 to report V_pin.

Per-channel chain

[TA — Sparrow Test Adapter R0]
   2.5 V (AMS1117)
     │
   R11..R14 (2.2 kΩ ±1 %)           ← TA pullup
     │
   J5 IDC pin (4 / 6 / 8 / 10)

[N-Top — Sparrow IDC N-Top R3]
   J5 IDC pin
     │
   D15 / D16 KGSOT05C TVS to GND    ← ESD only, reverse-biased ~nA leakage
     │
   LSHM J2 pin (31 / 32 / 33 / 34)
     │
   FE J2 pin

[FE — Sparrow Fixture Electronics R3]
   FE J2-31..34 (= GND_SW0..3_OUT)
     │
     ├── R175..R178 (2.2 kΩ 1 %) ─ Q4/Q5 2N7002DW drain ─ source ─ GND
     │   (gate ← GND_SW0..3 from PCA9506 I/O expander, 3.3 V logic)
     │   (R_DS_on ~5 Ω typ, ~10 Ω worst at V_GS = 3.3 V)
     │
     └── R235..R238 (100 K 1 %, VMEAS divider top)
                                       │
                                      mid
                                       ├── R241..R244 (100 K 1 %, bot) ─ GND
                                       └── R267..R270 (120 Ω LP) ─ ADS7828EB U40 ch4..7
                                           (ADC ×0.5 attenuator;
                                            software ×2 back to V_pin)

Key topology note: unlike the FE_MPIO test, the N-Top does not insert a 39 Ω + ADG4612 switch on these lines — only a TVS for ESD. So the path from TA to FE is essentially direct (modulo ribbon-cable resistance < 0.1 Ω, negligible).

Equivalent circuit at the J5 pin

With R_TA_pullup = 2.2 K to V_TA, the divider equation is:

V_pin = V_TA × R_loading / (R_TA + R_loading)

Corner math

Open switch (16 measurements)

V_pin = V_TA × 200 / (2.2 + 200) = V_TA × 0.9891

YAML window → 2.35 – 2.61 V (rounded outward to 1 cV).

Nominal is 2.47 V, not 2.5 V. This 27 mV downshift from "expected 2.5 V" is the 200 K parallel load on the 2.2 K pullup — about 1 % loss. Critical for production SPC: the open-switch distribution should centre at ~2.47 V; readings outside 2.35–2.61 V indicate real fault (loose TA connection, FE VMEAS short, broken pullup, etc.).

Closed switch (4 measurements)

R_par = (R_FE + R_DS_on) || R_VMEAS = (~2.21 K) || (~200 K) ≈ 2.18 K V_pin = V_TA × R_par / (R_TA + R_par)

YAML window → 1.17 – 1.33 V (rounded outward).

Nominal is 1.24 V, not 1.25 V. The 200 K VMEAS divider's small contribution to the bottom-side resistance pulls the midpoint down by ~6 mV from the "pure" 2.2 K + 2.2 K = 1.25 V centre. Negligible in absolute terms but should be reflected in SPC expectations.

Source documents

• Sparrow FE PCBA ESH10000540 R3 — schematic page 6 (Fixed Load + UART-RS485):
  • Q4, Q5 = 2N7002DW (EGP10000893) dual NMOS
  • R175..R178 = 2.2 kΩ 1 % (EGP10000081) — FE load resistors (gate-controlled)
  • R235..R238 = 100 K 1 % (EGP10000121) — VMEAS divider top
  • R241..R244 = 100 K 1 % (EGP10000121) — VMEAS divider bottom
  • R267..R270 = 120 Ω 1 % (EGP10000052) — LP filter to ADC
  • U40 = ADS7828EB (EGP10000946) — 12-bit ADC, ch4..7 used for fixed-load VMEAS
  • U7 = PCA9506BS (EGP10001232) — I/O expander, 3.3 V logic, drives GND_SW0..3
• Sparrow IDC N-Top PCBA ESH10000634 R3 — netlist NetList_Sparrow_FE_N-Top_R3.qcv:
  • LSHM J2-31..34 ↔ IDC J5-4/6/8/10
  • D15, D16 = KGSOT05C TVS only (no 39 Ω, no ADG4612 on this path)
• Sparrow Test Adapter ESH10000654 R0 — schematic:
  • R11..R14 = 2.2 kΩ 1 % (EGP10000081) — TA pullup to 2.5 V
  • U3 = AMS1117-ADJ (EGP10001062) — 2.5 V rail source (per D.03)
• PLEASE SIG-07 — fixed-load VMEAS chain spec: gain ±1.6 %, offset ±6 mV
• PLEASE D.03 — AMS1117 V_pullup tolerance (+3.5 % / −3.0 %)

Trade-offs: ## Tradeoffs accepted

Open-switch window widened from ±0.10 V to a corner-fit ±0.13 V (asymmetric: 2.35–2.61 V)

• Previous 2.40 – 2.60 V was too tight. At worst-low corner (V_TA = 2.425 V × 0.989 loading × 0.984 VMEAS gain − 0.006 offset = 2.354 V), a healthy unit at the AMS1117 floor + VMEAS spec edge would nuisance-fail. At worst-high (2.607 V), same problem on the upper bound.
• New 2.35 – 2.61 V matches the corner exactly. Catches:
  • Broken / missing TA pullup (V_pin → 0 V or floating ~ random) — caught
  • FE VMEAS shorted to GND (V_pin reads 0 V) — caught
  • Pullup-to-5 V short (V_pin reads ~5 V) — caught
  • Stuck FE NMOS ON (V_pin reads ~1.24 V) — caught (below 2.35 V floor)
  • Pure spec-edge drift (in-tolerance components) — passes correctly

Closed-switch window tightened from ±0.10 V to ±0.08 V (1.17–1.33 V)

• Previous 1.15 – 1.35 V was wider than the corner. The corner is 1.17–1.33 V; widening to ±0.10 V added a generous margin not justified by the chain math.
• New 1.17 – 1.33 V catches:
  • Stuck FE NMOS OFF (V_pin would read ~2.47 V instead of 1.24 V) — caught (way above 1.33 V)
  • Broken FE 2.2 kΩ load resistor (V_pin floats to pullup) — caught
  • Pure spec-edge drift — passes correctly

Nominal-value corrections in YAML inline comment

• Updated the comment from "1.25 V midpoint" / "full 2.5 V" to "1.24 V" / "2.47 V" with the explanation that the FE VMEAS 200 K divider loads the 2.2 K TA pullup by ~1 %. Future readers won't misinterpret the windows as "centred on 2.5 V".

Stack assumptions

• R_DS_on of Q4/Q5 modelled at 10 Ω worst-case at V_GS = 3.3 V (PCA9506 logic). 2N7002DW datasheet doesn't publish R_DS_on at V_GS = 3.3 V explicitly; conservative estimate based on V_GS = 4.5 V spec (5 Ω typ, 7.5 Ω max) extrapolated to a lower drive voltage. In practice, 10 Ω in series with 2.2 kΩ is < 0.5 % of the divider — negligible compared to the 1 % R tolerance.
• TA pullup R11..R14 tolerance assumed 1 %. EGP10000081 (2K2 0402) is the same code as on the FE side; FE is documented as 1 % tolerance in BOM, so TA assumed same.
• No per-fixture calibration. Limits derive from worst-case corners. If empirical SPC after ≥10 production runs shows the distribution clustering tightly at ~2.47 V / ~1.24 V with low spread, the windows could be tightened further with confidence.

What this test does NOT catch

• GND_SW signal degradation upstream of Q4/Q5 (e.g., I²C expander U7 partially failing such that GND_SW0..3 toggle slowly or get stuck mid-transition). The test only samples the steady-state V_pin after the runner sets GND_SW. A slow rise on GND_SW that makes the MOSFET partially ON during the sample would produce a reading between 1.24 V and 2.47 V — which would fall outside both windows and fail. Side effect: catches transition issues even without explicitly testing them.
• Per-channel cross-talk between J5_FIXED_LOAD channels. Each scenario reads all 4 channels and the runner expects exactly one closed and three open — but the test doesn't explicitly correlate the "other 3 channels stay at 2.47 V" with the active channel's switch state.

Follow-up actions

1. Update YAML limits — done (20 of 20 windows changed; 16 open + 4 closed).
2. Document derivation — done (this decision).
3. ~~Correct YAML inline comment with actual nominals (_{1.24 V, 2.47 V)} — done.
4. TODO: After ≥10 production runs, pull SPC stats:
   • Open-switch readings should cluster at 2.47 V (not 2.5 V). Cpk ≥ 1.33 within 2.35–2.61 V.
   • Closed-switch readings should cluster at 1.24 V (not 1.25 V). Cpk ≥ 1.33 within 1.17–1.33 V.
   • If distributions are tight, consider per-fixture calibration to tighten windows further.
5. TODO: Capture 2N7002DW (EGP10000893) in PLEASE with R_DS_on @ V_GS = 3.3 V curve, so the 10 Ω worst-case assumption is structured rather than estimated.
6. TODO: Cross-reference D.08 from any PLEASE test case (PT-SIG-07.*) that maps to a pt_code tag in fe_J5_fixed_load.yaml.

Chain topology (full path traced from netlists)

The J5 MPIO test exercises the AD5592R on the Sparrow N-Top (ESH10000535 R3) — not the FE-side AD5593Rs (which fe_J7_mpio_relay.yaml covers). The signals route as a passive pass-through across three boards plus the TA loopback.

Per-channel chain

[Sparrow N-Top — ESH10000535 R3]
   AD5592R (U10 or U22, 12-bit DAC/ADC, EGP10000891)
   DAC channel (one of IO0..IO7)
     │
     (Sparrow N-Top internal routing — may include PS509LEX
      analog mux U2/U3/U12/U25; R_DS_on ~150 Ω, sub-mV at HiZ ADC)
     │
     → Agent backplane → AccordionA2 host
     │
[FE — Sparrow Fixture Electronics R3]
   J10 LSHM pin (Agent-facing, EGP10001595 LSHM-120):
     pin 13 ↔ MPIO_1, pin 14 ↔ MPIO_3,
     pin 15 ↔ MPIO_0, pin 16 ↔ MPIO_2
     │
     ── wire pass-through (no active components, no series R) ──
     │
   J2 LSHM pin (IDC-N-Top-facing, EGP10001411 AXK5S60047):
     pin 21 ↔ MPIO_0, pin 22 ↔ MPIO_1,
     pin 23 ↔ MPIO_2, pin 24 ↔ MPIO_3
     │
[IDC N-Top — ESH10000634 R3]
   J2 LSHM pin (21..24)
     │
   D9 / D10 KGSOT05C TVS to GND (ESD only, reverse-biased ~nA leakage)
     │   (NO 39 Ω series R, NO ADG4612 switch on this path —
     │    unlike FE_MPIO_2..11 which DO go through that chain.)
     │
   IDC J5 pin: 3 (MPIO_0), 5 (MPIO_1), 7 (MPIO_2), 9 (MPIO_3)
     │
[TA — Sparrow Test Adapter R0]
   J5-3 ↔ J5-7  (MPIO_0 ↔ MPIO_2 loopback short)
   J5-5 ↔ J5-9  (MPIO_1 ↔ MPIO_3 loopback short)
   (NO pullup, NO load, NO divider — just the shorts)

Test sequence (per pair, e.g. 0↔2)

1. Configure MPIO_0 as DAC, drive 4.0 V (or 0.5 V).
2. Configure MPIO_2 as ADC, read back. (= *_A_4V_B / *_A_0V5_B)
3. Configure MPIO_1 and MPIO_3 as ADC, read crosstalk while 4 V is held.
4. Swap roles: MPIO_2 drives, MPIO_0 reads. (= *_B_4V_A / *_B_0V5_A)

Tolerance stack

The DAC and ADC errors compound (independent error sources, even though both are on the same AD5592R chip — different channels, different gain/offset paths). Vref drift cancels in loopback.

Passive chain elements (TVS, PS509LEX, ribbon) contribute sub-mV at HiZ ADC current, dominated by the AD5592R DAC + ADC accuracy.

Corner math

V_read = V_set × DAC_gain × ADC_gain ± DAC_offset ± ADC_offset

Combined chain: gain ±0.6 %, offset ±16 mV (worst case, sequential).

Drive 4.0 V

YAML window → 3.96 – 4.04 V.

Drive 0.5 V

YAML window → 0.48 – 0.52 V.

INIT (idle)

DAC at 0 V (or HiZ + pulldown chain). ADC reads with its own offset only — DAC contribution at 0 V is 0 V × gain = 0. Worst-case ±8 mV (SIG-01 offset). Current YAML ±0.01 V matches with 2 mV margin. Kept.

Crosstalk (other 2 channels read while 4 V is driven on one channel)

Physical DC crosstalk between MPIO channels through the ribbon-cable parasitic R is sub-mV (each channel has its own DAC drive and ADC read; no shared current path). The ±0.1 V window allows for AC capacitive coupling during the drive transient + a wide margin. Kept.

Difference from D.07 (fe_J7_mpio_relay Step 1)

D.07 and D.09 produce identical windows because the loopback chain shape is the same (DAC → passive → loopback short → passive → ADC). The differences are:

The chain accuracy spec (SIG-01 per direction) is the same, so the corner windows are the same.

Source documents

• Sparrow N-Top PCBA ESH10000535 R3 — BOM (PartsList_Sparrow_NTop_R3.csv): U10, U22 = AD5592R (EGP10000891)
• Sparrow Fixture Electronics ESH10000540 R3 — netlist (NetList_Sparrow_FE_R3.qcv): MPIO_0..3 = J10-15/13/16/14 (Agent) ↔ J2-21/22/23/24 (IDC N-Top), pure wire pass-through
• Sparrow IDC N-Top ESH10000634 R3 — netlist (NetList_Sparrow_FE_N-Top_R3.qcv): J2-21..24 ↔ J5-3/5/7/9 via D9/D10 KGSOT05C TVS only
• Sparrow Test Adapter ESH10000654 R0 — schematic shows J5-3↔J5-7 and J5-5↔J5-9 loopback shorts (no pullup, no load on the J5 MPIO pins)
• PLEASE SIG-01 — MPIO 4-channel chain accuracy: ±0.3 % gain, ±8 mV offset
• PLEASE D.07 — same shape derivation for FE_MPIO loopback (Step 1)

Trade-offs: ## Tradeoffs accepted

Drive 4 V / 0.5 V windows widened to chain corner

• Previous 3.98–4.02 / 0.49–0.51 V windows were half the chain corner. Same root cause as D.07: the assumption that single-direction SIG-01 accuracy applies to a loopback read is wrong. The DAC contribution + ADC contribution compound.
• New windows match the corner exactly. Catches:
  • Open DAC channel (V_read = 0 V or rail) — easily flagged
  • Failed TA loopback short (V_read = floating, typically rail or driven by leakage) — flagged
  • DAC stuck at wrong code — caught
  • Pure linearity / offset drift within SIG-01 spec — passes correctly

INIT, crosstalk kept

• Already at SIG-01 offset bound (±0.01 V) and practical capacitive-coupling allowance (±0.1 V) respectively. No reason to change.

Sparrow N-Top PS509LEX analog mux not modelled explicitly

• I noted in the chain that the Sparrow N-Top internal routing may include PS509LEX analog mux switches between the AD5592R and the output connector. The R_DS_on of PS509LEX (~150–200 Ω) is in series with the channel, but at the loopback partner's HiZ ADC input, no current flows → sub-mV drop → doesn't affect DC accuracy.
• Did not trace the Sparrow N-Top schematic in detail. If the N-Top has additional series elements (e.g. ESD diodes, attenuators) that DO affect DC, the windows would need adjustment. Will revisit if production data shows systematic offset.

Same chain corner as D.07 → same window

• D.09's drive-4V window (3.96–4.04 V) is identical to D.07's. Production SPC implication: both tests should show similar distributions on healthy units. If one test passes 4.0 V loopback and the other consistently fails, the issue is in the test-specific chain (Sparrow N-Top vs FE AD5593R), not in the AD5592R/AD5593R DAC/ADC accuracy itself.

What this test doesn't catch

• PS509LEX stuck OFF on the Sparrow N-Top. If PS509LEX is in the path and gets stuck OFF, the loopback would fail entirely (DAC drive doesn't reach the J5 pin → reading floats). The test would catch this as a wildly out-of-window reading, but wouldn't distinguish "PS509LEX stuck" from "DAC stuck" from "loopback short broken". Diagnosis requires probing the Sparrow N-Top output pins directly.
• Sparrow N-Top to Agent connector contact issues. Same as above: any break in the path produces an out-of-window reading but doesn't tell you where.

Follow-up actions

1. Update YAML limits — done (8 of 20 windows changed; 12 kept).
2. Document derivation — done (this decision).
3. TODO: Trace the Sparrow N-Top schematic in detail — confirm whether MPIO_0..3 from AD5592R route through PS509LEX, and if so, document the per-channel R_DS_on contribution. Capture the AD5592R (EGP10000891) and PS509LEX (EGP10001572) in PLEASE via please_component_update with structured properties.
4. TODO: After ≥10 production runs through fe_J5_mpio, pull SPC stats:
   • Drive 4 V Cpk ≥ 1.33 within 3.96–4.04 V.
   • Drive 0.5 V Cpk ≥ 1.33 within 0.48–0.52 V.
   • Compare distribution to fe_J7_mpio_relay Step 1 (FE_MPIO_0..7 loopback). Significant systematic offset between the two would indicate either chip-family difference (AD5592R vs AD5593R) or unmodelled chain element (e.g. PS509LEX).
5. TODO: Cross-reference D.09 from any PLEASE test case (PT-SIG-01.*) that maps to a pt_code tag in fe_J5_mpio.yaml.

Chain topology

The PWM test exercises the ATMEGA4809 (U18 on Sparrow N-Top ESH10000535 R3) PWM peripheral outputs. The signals route as a passive pass-through (similar to the J5_FIXED_LOAD and J5_MPIO paths — no 39 Ω + ADG4612 chain, just TVS on the IDC N-Top).

Per-channel chain

[Sparrow N-Top — ESH10000535 R3]
   ATMEGA4809 U18 PWM peripheral (PWM_0, PWM_1)
     │
     (Sparrow N-Top internal routing — pure digital pass-through
      to LSHM connectors going to Agent backplane)
     │
[FE — Sparrow Fixture Electronics R3]
   FE pass-through — no active components on the PWM path
     │
[IDC N-Top — ESH10000634 R3]
   TVS only (KGSOT05C, reverse-biased, ~nA leakage)
   No 39 Ω series R, no ADG4612 switch
     │
   IDC J5-13 (PWM_0), J5-14 (PWM_1)
     │
[TA — Sparrow Test Adapter R0]
   J5-13 → routed to host MPIO_18
   J5-14 → routed to host MPIO_27
     │
[Host AccordionA2 — read via SIG-01 MPIO chain]
   Host MPIO is high-impedance (≥1 MΩ pulldown) → V_OH at pad ≈ V_SET (no driver drop)

V_SET sweep values come from the EXT_VIO programmable rail (per PWR-07): 1.5, 1.8, 2.5, 3.3 V — each with ±1.6 % tolerance.

Tolerance stack

Corner math — STATIC_HIGH

V_read = V_SET × (1 ± 0.016) × (1 ± 0.003) ± 0.008 V

These match the previous YAML windows within ~12 mV (current was a flat ±2.5 % formula slightly wider than the corner at higher V_SET, essentially identical at 1.5 V). Tightening to corner-match catches small drift without losing real-fault sensitivity.

Corner math — STATIC_LOW

V_OL at HiZ load is essentially 0 mV (no current to drop voltage across the PWM driver's pulldown). With MPIO offset ±8 mV:

• Worst-low reading: −8 mV (ADC offset only; driver can't drive negative)
• Worst-high reading: +50 mV (allows ~40 mV V_OL margin for partial-conduction faults + ±8 mV offset)

YAML window → −0.01 to +0.05 V (rounded outward).

Previous 0.0 – 0.1 V window allowed up to +100 mV which is wider than the corner. Tightening to +0.05 V catches a stuck-mid or partially-conducting PWM driver earlier.

50PCT_AVG and ACTUAL_FREQ — kept

50PCT_AVG (duty = 0.5 @ 10 kHz, V_SET = 3.3 V)

Nominal V_avg = V_SET / 2 = 1.65 V. Chain corner (assuming exact 50 % duty): 1.59 – 1.71 V (±60 mV).

YAML window 1.50 – 1.80 V (±150 mV) is intentionally wider — accommodates:

• PWM ripple residue at the host MPIO (10 kHz fundamental + harmonics, partial RC filtering)
• Duty-cycle quantization in the ATmega PWM peripheral (depending on prescaler / TOP value, exact 50 % may be off by half-LSB)
• Integration-window mismatch between the host sampling and the PWM period

These practical effects aren't easily corner-derived from datasheet specs. The wide window is appropriate for this measurement. Kept.

ACTUAL_FREQ_HZ

Crystal-based ATmega is ppm-accurate; the actual reading should be 10000 ± 1 Hz on a healthy unit. The YAML's ±5 % window (9500 – 10500 Hz) is intentionally generous — it's a gross-fault detector: catches "peripheral didn't initialise", "register write missed", "wrong PWM channel selected", "PWM not enabled", etc. Kept.

Source documents

• Sparrow N-Top PCBA ESH10000535 R3 — BOM (PartsList_Sparrow_NTop_R3.csv): U18 = ATMEGA4809 (EGP10001000) for PWM/Tach peripheral
• Sparrow Fixture Electronics ESH10000540 R3 — pass-through for PWM signals
• Sparrow IDC N-Top ESH10000634 R3 — netlist: PWM_0/PWM_1 route through KGSOT05C TVS only (no 39 Ω, no ADG4612)
• Sparrow Test Adapter ESH10000654 R0 — routes J5-13 → host MPIO_18, J5-14 → host MPIO_27
• PLEASE SIG-04 — PWM 2-channel spec: 1 Hz – 1 MHz; duty 0–100 %; VCCO 0–3.3 V; V_OH ≥ 2.9 V @ 3.3 V / 10 mA; V_OL ≤ 0.33 V @ 3.3 V / 10 mA
• PLEASE PWR-07 — EXT_VIO programmable rail: 0–3.3 V, ±1.6 % of set
• PLEASE SIG-01 — host MPIO chain accuracy: ±0.3 % gain, ±8 mV offset
• ATMEGA4809 datasheet (EGP10001000) — PWM peripheral spec, crystal-based timing

Trade-offs: ## Tradeoffs accepted

STATIC_HIGH tightened from ±2.5 % flat formula to corner-derived

• Previous flat ±2.5 % window was slightly wider than the corner at higher V_SET (e.g. at 3.3 V the YAML was ±82.5 mV vs corner ±71 mV). The extra margin had no derivation behind it.
• New corner-derived windows match the ±1.6 % rail ⊕ MPIO chain corner exactly. Catches:
  • Wrong V_SET rail selected (e.g. 1.8 V rail used when 2.5 V expected) — caught (way outside any setpoint window)
  • Rail at spec edge passes correctly
  • PWM driver permanently low or floating (V_read ≈ 0 V or pull) — caught
  • Subtle drift just outside ±1.6 % rail spec or ±0.3 % MPIO gain — caught
• Difference from previous: ~12 mV per side at 3.3 V down to ~1 mV per side at 1.5 V. Small in absolute terms but represents the actual chain corner.

STATIC_LOW tightened from 0.0–0.1 V to −0.01/+0.05 V (asymmetric)

• Previous 0.0 – 0.1 V allowed up to 100 mV — much wider than the physical corner. A PWM driver that's stuck at ~80 mV (partial conduction, leaky output stage, soft short to a small bias network) would pass the old window.
• New −0.01 to +0.05 V matches the corner: ADC offset can produce negative readings (bound at −8 mV), driver V_OL at HiZ should be at most a few mV (well within +50 mV).
• Asymmetric: low bound at −0.01 (just past ADC offset) instead of 0.0, since the physical V can't go negative — only measurement offset can.

50PCT_AVG kept at ±9 % window

• Practical PWM-averaging effects dominate the measurement. Tightening to the chain corner (±60 mV) would risk nuisance fails from:
  • Imperfect filtering of 10 kHz ripple at the host MPIO (RC time constant must be ≫ PWM period for clean averaging)
  • ATmega PWM duty-cycle quantization (8-bit timer at 10 kHz with 16 MHz clock gives ~6-bit effective duty resolution, so duty=50 % might actually be 49–51 %)
  • Sampling-window vs PWM-period mismatch
• Future tightening possible with empirical SPC data. If production runs show a tight distribution at exactly 1.65 V ± 30 mV, the window could shrink to e.g. 1.55 – 1.75 V.

ACTUAL_FREQ kept at ±5 % window

• The window is for gross-fault detection, not parametric drift. Crystal-based ATmega is ppm-accurate; any healthy reading is 10000 ± 1 Hz.
• A reading outside ±5 % indicates a real systemic failure: peripheral didn't initialise, register write missed, wrong PWM channel enabled, oscillator failed.
• Tightening to ±0.1 % (still very generous vs crystal accuracy) would be a meaningful upgrade — but the ±5 % gross-fault catch is already doing what the test needs.
• Future tightening to ±0.1 % worth considering if a frequency-drift mode is ever a real failure mode worth catching.

V_SET assumed to be EXT_VIO

• The YAML comment doesn't explicitly state which rail provides V_SET = 1.5 / 1.8 / 2.5 / 3.3 V. I assumed EXT_VIO (PWR-07) because these are exactly the EXT_VIO sweep setpoints. If V_SET is actually a different rail (e.g. ATmega's own VCC), tolerance would differ:
  • EXT_VIO: ±1.6 % per PWR-07 (used here)
  • ATmega VCC if 3.3 V system rail: ±5 % typically — would make the window much wider
• Assumption is the natural one given the EXT_VIO sweep is the only test infrastructure that produces those exact setpoints in production. Verify by checking the Python runner module.

Outward rounding choices

• STATIC_HIGH limits use 3-decimal precision (±1 mV) matching the corner exactly. No outward rounding margin since the corner already accounts for worst-case spec.
• STATIC_LOW upper bound 0.05 V chosen as a "catch partial-conduction faults" practical threshold rather than strictly corner-derived (corner says < 0.01 V).

Follow-up actions

1. Update YAML limits — done (10 of 14 windows changed; 4 kept).
2. Document derivation — done (this decision).
3. TODO: Verify V_SET sweep source in fe_J5_pwm.py runner. Confirm V_SET = EXT_VIO (the assumption underlying the ±1.6 % tolerance). If V_SET comes from a different rail with different tolerance, the STATIC_HIGH windows need adjustment.
4. TODO: After ≥10 production runs through fe_J5_pwm, pull SPC stats:
   • STATIC_HIGH at each V_SET — confirm Cpk ≥ 1.33 within the new (corner-tight) windows.
   • 50PCT_AVG — measure typical spread. If it's tight (e.g. ±30 mV), consider tightening the YAML window to match.
   • ACTUAL_FREQ — confirm readings cluster at 10000 ± 1 Hz. Consider tightening to ±100 Hz (still 10× the typical spread) for better fault sensitivity.
5. TODO: Capture ATMEGA4809 (EGP10001000) in PLEASE via please_component_update with PWM peripheral specs (duty resolution, frequency accuracy from crystal).
6. TODO: Cross-reference D.10 from any PLEASE test case (PT-SIG-04.*) that maps to a pt_code tag in fe_J5_pwm.yaml.

Need 20 units, only 1 on hand (gap −19). Build order still outstanding as of 2026-05-15. Longest lead time on critical path. See PRODUCTION_READINESS.md §3.4 and §4 G-01.

Need doubled by 2026-05-12 scope expansion (20 systems + 20 standalone). Order must cover 40 pcs. Blocks final assembly + standalone deliverables. See PRODUCTION_READINESS.md §4 G-05.

Need 20, on hand 18 → order at least 2. Minor shortfall. See PRODUCTION_READINESS.md §3.1, §4 G-06.

Need 19 pcs ESH10000158 R5 (externally built PCBA) for the 19 ESH10000182 builds. No order in MES yet. If no R5 order placed and R6 sidetrack slips, the 19-piece shortfall blocks the entire ESH10000182 build (and therefore all 19 units of ESH10000633). Decision options: (a) place R5 order ≥19 pcs now, or (b) confirm R6 sidetrack timing by Week 4. Hard deadline 2026-05-27. See PRODUCTION_READINESS.md §4 G-13 and §6 risk register.

Symptom: On power-up Sparrow N-Top LEDs sometimes red (fault). Reseating the two ESH10000538 M2base loopbacks on the Accordion base usually recovers normal operation. Intermittent.

Status: Open investigation. Not yet root-caused. Workaround = reseat until LEDs green.

Production impact: Cannot ship units that need loopback reseating to boot. Must be reproducible/debuggable before PRODUCTION_TEST_PROCEDURE.md is finalised.

Production target rev change (2026-05-12): ESH10000538 moved R0 → R1. R1 at Manufacturing in MES; externally built; 100 pcs on order ETA 2026-05-29. 15 R0 pcs on hand decided as scrap (2026-05-15).

Open question: does the R1 design address the SPI/loopback intermittency observed on R0? If yes, ISSUE-001 may resolve by switching to R1 stock. If no, investigation continues independently.

Verification checklist: PCB thickness measurement; gold-finger inspection; SODIMM socket inspection; SPI scope capture during failing boot; Enable-signal startup sequence documentation; per-board reproduction test.

See ISSUES/ISSUE-001_M2base_loopback_SPI_intermittent.md for full hypothesis tree and update log. Hypotheses tracked as ASM-01..ASM-03.

SYS-07 (production test must exercise every user-accessible pin) is currently violated for 5 functional groups. Cross-check derived from Sparrow Hardware Datasheet v3 §4 against Maestro orchestrator tests/fixture-electronics-test.yaml.

Hard gaps (5):

Optional gap (1): PSU Phoenix outputs (VPSU_0/1, VSENSE±_0/1) — only if PSU M.2 module fitted. Gate any future test on a precondition.

Closure path: create the 5 sub-tests, wire them into fixture-electronics-test.yaml, tag each step with the listed pt_code:. Once please_coverage_gap projectId=1 shows zero gaps in these functional groups, this notice can be resolved.

Linked to requirement SYS-07 (id 67).

What: Verification record id 18 (PT-SIG.04, testCaseId 28) closed as fail.

Measurement: J6_MIC_LOAD_BIAS_L_DUT_L_NEG = 1.9598 V Limit: ≤ 1.95 V (upper) Overshoot: +9.8 mV / +0.5 % Source: Maestro fixture-electronics-test exec 0176faa8-1370-40c0-bed8-d7a736c20fad 2026-05-22T13:13:47Z.

Requirements affected:

• SIG-08 (Audio Load — phantom/bias)
• SIG-11 (AUDIO_GND ↔ system GND galvanic link)

Both flip from Covered → failingVerifications. Plan approval gated until this is resolved (either retest → pass, or formal deviation with rationale).

Spec vs measurement mismatch:

• PT-SIG.04 spec: signal MIC_IN_L, nominal 2.273 mA, tolerance ±2.3 %.
• Failing measurement: J6_MIC_LOAD_BIAS_L_DUT_L_NEG, value in V.

The names are related (both audio-bias-load) but the units differ. Either: (a) the Maestro step is measuring the voltage across the bias-load circuit while the PT-* spec is targeting the current — both valid, but the two limits then need separate PT-* cases; or (b) the Maestro step + PT-SIG.04 are intended to be the same check and one or both spec/limit numbers need a reconciliation.

Tracked as Q-AUDIO-001 for investigation. Closure path (per prepare_sign_off workflow step 2): either retest the unit on a known-good fixture, or capture a formal please_deviation_add + decision if the +0.5 % overshoot is acceptable.

ISSUE-001 root cause is ESH10000538 R0 PCB thickness out of SODIMM tolerance, causing marginal contact pressure on edge fingers and intermittent SPI signal integrity.

Risk if wrong: If wrong, ISSUE-001 may persist in the new ESH10000538 R1 stock (100 pcs incoming) if R1 doesn't address PCB thickness. Could surface in production test and block 20-unit delivery.

ISSUE-001 root cause is wear, contamination, or plating defect on either the SODIMM socket on the Accordion base or the gold-finger edge of ESH10000538 R0.

Risk if wrong: If wrong but believed, mechanical replacement/refurbishment effort is wasted. If true and unaddressed, the issue follows board-handling lifecycle (re-emerging as sockets/PCBs wear), not just R0 design.

ISSUE-001 root cause is non-deterministic SPI startup sequencing — SPI traffic begins before loopback path / downstream device enables are fully stable, causing host to latch a fault state and drive LEDs red. Reseating triggers a cold restart with different timing, masking the underlying SI as the real cause.

Risk if wrong: If wrong, firmware/enable sequence fixes won't help. If true, all stock revisions (R0 and R1) and even new boards will exhibit the issue until a settle window is enforced in firmware. Production yield risk.

J6 audio bias-load: marginal voltage overshoot — root cause + spec reconciliation

Failure observed

J6_MIC_LOAD_BIAS_L_DUT_L_NEG = 1.9598 V vs upper limit 1.95 V (+0.5 %, +9.8 mV) during exec 0176faa8 (2026-05-22).

Open questions

1. Reproducibility. Is this a one-off measurement noise event, or does the unit consistently sit at ~1.96 V across multiple runs? Suggested action: re-run the J6 audio step ≥5 times on the same DUT + fixture; record the min/mean/max.

2. Fixture vs DUT origin. If reproducible, swap to a second fixture. If second fixture also shows ~1.96 V, the bias-load circuit on the DUT is the source. If second fixture reads in spec, the original fixture's bias resistor / reference is drifting.

3. Spec / Maestro reconciliation (unit mismatch). PT-SIG.04 specifies MIC_IN_L = 2.273 mA ± 2.3 %. The failing measurement is in volts. Decide:

   • Option A: PT-SIG.04 and the Maestro step test different quantities (voltage across bias network vs MIC_IN_L current). Add a second PT-* case (PT-SIG.04B?) with the V-based limit; PT-SIG.04 keeps the mA target.
   • Option B: They're the same check expressed differently. Convert one to the other (1.9598 V across the bias resistor + known R = derived current); update spec or Maestro step to align.

4. Limit derivation. Where does the 1.95 V upper limit come from? Sparrow Hardware Datasheet §? Test development heuristic (mean + 3σ from earlier runs)? If the latter, the +0.5 % overshoot may simply mean the limit was tightened too aggressively after a small sample.

5. Deviation acceptability. If root-causing is impractical before sign-off: is +0.5 % audio bias-load voltage acceptable for production? Need an explicit decision (with rationale) captured via please_decision_create per the prepare_sign_off workflow.

Closure criteria

• Q-AUDIO-001 closes when one of: (a) retest passes consistently and the original fail is documented as transient; (b) deviation captured with formal decision + rationale; (c) limit revised based on documented spec/derivation update.

Due: 2026-06-08

Sparrow system-level interfaces cannot be frozen until ESH10000540/543/634 sub-modules complete their R-rev sign-offs. Tracking as a release gate.