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Sparrow complete product

ESH10000633 · Rev R1

in_progresselectronics

System-level Sparrow product. Test implementation lives in Maestro TAT package ESH10000633_SparrowUnitTest_v01 (https://github.com/esharpab/testdevelopment-esharp-tat-registry-ESH10000633_SparrowUnitTest_v01).

0% Coverage
0% Done
0 Requirements
67 Test Cases
3 Blockers
9 Open Entries

Timeline

Color = derived gate state · hover a tile for its note.
marker
Gate 1 — Design Release (all sub-assemblies at Manufacturing in MES; ESH10000634 R3 approved)
May 15, 2026
marker
Gate 2 — Inventory Procurement (all shortfalls resolved; ESH10000182 build order confirmed)
Jun 5, 2026
marker
Gate 3 — Test & Production Infrastructure (ESH10000654 verified; test procedure complete; DUT serials defined)
Jun 5, 2026
marker
Gate 4 — First Article (S/N 001 assembled and passed production test)
Jun 12, 2026
marker
Gate 5 — Production Run (20 systems assembled + standalone deliverables 10×636, 20×614, 20×637, 20×EPN1000786)
Jul 6, 2026
marker
Gate 6 — Delivery (final QC, packaging, delivery documentation complete)
Jul 13, 2026
not started
🏁 Release
· 2/6

Status & gates

Chronological — Release is the final gate. Derived & read-only; edit via please_milestone_* tools.
MS-G1Gate 1 — Design Release (all sub-assemblies at Manufacturing in MES; ESH10000634 R3 approved) markerdue 2026-05-15
MS-G2Gate 2 — Inventory Procurement (all shortfalls resolved; ESH10000182 build order confirmed) markerdue 2026-06-05
MS-G3Gate 3 — Test & Production Infrastructure (ESH10000654 verified; test procedure complete; DUT serials defined) markerdue 2026-06-05
MS-G4Gate 4 — First Article (S/N 001 assembled and passed production test) markerdue 2026-06-12
MS-G5Gate 5 — Production Run (20 systems assembled + standalone deliverables 10×636, 20×614, 20×637, 20×EPN1000786) markerdue 2026-07-06
MS-G6Gate 6 — Delivery (final QC, packaging, delivery documentation complete) markerdue 2026-07-13
Release / Readiness not started 2/6 met
pending Requirements approved
  • PWR-26: draft
  • PWR-31: draft
  • PWR-12: draft
  • PWR-13: draft
  • PWR-15: draft
  • SIG-14: draft
  • SIG-04: draft
  • SIG-06: draft
  • SIG-05: draft
  • SIG-07: draft
pending Coverage ≥ 100%
  • No requirements in scope
pending All test cases pass
  • 25/67 passed
  • 42 not yet run
pending No blocking issues open
  • E-001: open blocker
  • E-004: open blocker
  • E-022: open blocker
met Deviations resolved
met Interfaces frozen
Blocked 3 blocking entries
🔗 Composition 6 dependencies need attention: ESH10000534 R4 (amber), ESH10000535 R3 (amber), ESH10000536 R2 (amber), ESH10000540 R3 (amber), ESH10000543 R2 (amber), ESH10000634 R3 (amber)

Test Cases

25 Pass 0 Fail / Deviated 0 N/A 42 Open3 / 67 Maestro impl.

Coverage — 0.0% · Done — 0.0%

74 of 74
CodeTitleCategoryCoverageStatus
COM-01 I2C Controller end-to-end Communication
COM-02 I2C fast-mode operation Communication
COM-03 I2C Device EEPROM 24AA02UID Communication
COM-04 SPI AD5592R devices accessible Communication
COM-05 RS485 full-duplex Communication
COM-06 I2C Controller signal levels (EXT_VIO-relative) Communication
COM-07 I2C onboard pull-ups + VDDA_SEL coordination Communication
COM-08 RS485 differential measurement + electrical limits Communication
COM-09 RS485 fault protection + fail-safe bias Communication
COS-01 Power LED Cosmetic
COS-02 RS-232 LED Cosmetic
COS-03 User LEDs (LP5012) respond Cosmetic
FW-01 ATmega MCU on I2C Firmware
FW-02 IDPROM writable Firmware
PWR-01 Common 12V rail Power
PWR-02 Common 5V rail Power
PWR-03 12V_EXT external rail Power
PWR-04 3V3_EXT external rail Power
PWR-05 1V8_EXT external rail Power
PWR-06 VADJ programmable rail Power
PWR-07 EXT_VIO programmable rail Power
PWR-08 VREF precision reference Power
PWR-09 External rails OCP Power
PWR-10 External rail VMEAS accuracy Power
PWR-11 External rail IMEAS accuracy Power
PWR-12 N-Top +18V rail Power
PWR-13 N-Top −18V rail Power
PWR-14 PoE input range Power
PWR-15 PoE maximum output power Power
PWR-16 PoE VMEAS accuracy Power
PWR-17 PoE IMEAS accuracy Power
PWR-18 Active Load source voltage range Power
PWR-19 Active Load sink current (IDC) Power
PWR-20 Active Load sink current (Phoenix) Power
PWR-21 Active Load energy limit Power
PWR-22 Active Load VMEAS accuracy Power
PWR-23 Active Load IMEAS accuracy Power
PWR-24 PSU (optional) range and accuracy Power
PWR-25 Common 12V / 5V rail current protection Power
PWR-26 External rail OCP transient blanking + fast-trip Power
PWR-27 External rail slew control (SRON) + bleed-out Power
PWR-28 PoE Class 1–8 support + 2-pair/4-pair delivery Power
PWR-29 PoE polarity indication LED Power
PWR-30 PoE port-power limits, classification + protection Power
PWR-31 Active Load protection mechanisms Power
REQ-EL-001 RoHS Compliance compliance
REQ-EL-002 REACH / SVHC Declaration compliance
REQ-EL-003 EMC Compliance compliance
REQ-EL-004 Operating Temperature Range environmental
REQ-EL-005 ESD Protection robustness
REQ-EL-006 CE Marking Applicability compliance
REQ-EL-007 Test Limit Derivation Documented quality
SIG-01 MPIO 0–5 V (4 channels) Signal
SIG-02 FE_MPIO OV-protected (12 channels) Signal
SIG-03 Differential AIN precision (8 channels) Signal
SIG-04 PWM programmable (2 channels) Signal
SIG-05 Tach input (2 channels) Signal
SIG-06 Relay driver low-side (4 channels) Signal
SIG-07 Fixed Load 2.2 kΩ (4 channels) Signal
SIG-08 Audio Load (phantom/bias) Signal
SIG-09 Tampering latch-and-hold (2 channels) Signal
SIG-10 USR_GPIO functional Signal
SIG-11 AUDIO_GND ↔ system GND galvanic link Signal
SIG-12 MPIO floating-input pulldown Signal
SIG-13 FE_MPIO fault-protected analog switches Signal
SIG-14 Differential AIN PGA gain settings + auto-scale Signal
SIG-15 MPIO/FE_MPIO load constraints for full accuracy Signal
SYS-01 Sub-assemblies installed and seated System
SYS-02 Fixture Link silkscreen revision marking System
SYS-03 Power-on from 20 V DC via Fixture Link eFuse System
SYS-04 PoE subsystem accepts 44–57 V isolated input System
SYS-05 Sparrow Fixture Electronics PCBA dimensions System
SYS-06 Accordion Agent enclosure dimensions System
SYS-07 Production test must exercise every user-accessible pin System