SYS-07 — Production test must exercise every user-accessible pin

Every user-accessible pin defined in Sparrow Hardware Datasheet §4 (J4–J9 IDC connectors, Audio DSUB-9, Active Load Phoenix headers, PSU Phoenix headers, PoE) shall be exercised by at least one production test step in fixture-electronics-test, with traceability from each Maestro step (pt_code) back to the pin functional group it covers.

Pin inventory per Sparrow Hardware Datasheet v3 §4 (sourceRef: 01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf): J4 — 8 differential AIN channels (AIN_P/N_CH1..8, 16 pins), 5V/12V/GND; J5 — MPIO_0..3 (4), FIXED_LOAD_0..3 (4), TACHO_0..1 (2), PWM_0..1 (2), LATCH_0..1 (2), VREF (1 net, 2 pins), 5V/12V/GND; J6 — MIC_IN_L/_/R/ (4 pins), LINE_OUT_L/_/R/ (4 pins), AUDIO_GND (8 pins one net), 5V/12V/GND; J7 — FE_MPIO_0..11 (12), RELAY_1..4 (4), 5V/12V/GND; J8 — VLOAD_POS_0/1, VLOAD_NEG_0/1, VREM_0/1, VPSU_0/1, VSENSE+_0/1, VSENSE-_0/1, 5V/12V/GND; J9 — SCL_SLV, SCL_MSTR, SDA_SLV, SDA_MSTR, EXT_VIO, RS485_RX±, RS485_TX±, 1V8_EXT, 3V3_EXT, 12V_EXT, VADJ, 5V/12V/GND; Audio DSUB-9 — LINE_OUT_L/_/R/, MIC_IN_L/_/R/, AUDIO_GND (mirrors J6 nets); Active Load Phoenix — VLOAD_POS_0/1, VREM_0/1, VLOAD_NEG_0/1; PSU Phoenix (optional) — VPSU_0/1, VSENSE+_0/1, VSENSE-_0/1, GND; PoE — PWR, GND. Each functional group above must map to ≥1 PT-* test case; the fixture-electronics-test orchestrator must invoke a sub-test that exercises each group; gaps tracked via please_coverage_gap.