Mini-PSU
ESH10000662 · Rev R1
Generated 2026-10-24 22:35 UTC
2-channel programmable buck-boost PSU Comtop Module. LT3942-based converters, 20V input, 0–24V/1.5A per channel output, DAC-controlled (VSET/ISET via AD5593R). VMON1/VMON2 output monitoring, PWM1n/PWM2n GPIO outputs via PI4IOE5V6416 expander. R1 adds VMON monitoring (ECO-012/013) and PWM expander relocation (ECO-010/011).
Coverage
100%
Done
50%
Requirements
6
Test Cases
25
Records
89
Blockers
1
Milestones
No milestones defined.
Items (3)
| Code | Status | Severity | Kind | Title | Date |
|---|---|---|---|---|---|
| E-009 | open | blocking | notice | BLOCKING: REQ-002 (1.5A/ch @ 24V) not demonstrated — R17/R49 rework pending | 2026-05-27 |
| E-010 | open | warning | decision | Rename OUT1n/OUT2n → OUT1_N/OUT2_N | 2026-05-27 |
| E-008 | open | info | notice | R24/R58 38.3kΩ applied to DUT-01 — BOM and ECO-015 not yet updated | 2026-05-27 |
Requirements
| Code | Status | Category | Title | Statement | Acceptance |
|---|---|---|---|---|---|
| REQ-001 | approved | Performance | Maximum output voltage 24V per channel | The device shall provide a maximum output voltage of 24V per channel. | VPSU ≥ 24.0V measured at no load with VSET at DAC maximum (5V). |
| REQ-002 | approved | Performance | Maximum continuous output current 1.5A per channel | The device shall provide a maximum continuous output current of 1.5A per channel. | Load sweep stable at 1.5A per channel at maximum VOUT (24V); VPSU remains within ±2% of setpoint (23.52–24.48V) throughout sweep. Both channels active simultaneously. |
| REQ-003 | approved | Performance | PCB hotspot ≤ 50°C at full load | The device shall not exceed 50°C (case / PCB hotspot) at full load and 25°C ambient. | Thermal measurement at VOUT=24V, ILOAD=1.5A per channel (both channels active), 25°C ambient; no point on case or PCB exceeds 50°C after thermal soak (30 min minimum). Measure at L1, L2, U1, U3, L3, L4. |
| REQ-004 | approved | Performance | Output voltage drift ≤ ±0.1% over 8 hours | Output voltage drift shall not exceed ±0.1% over 8 hours of continuous operation. | VOUT measured at t=0 and t=8h; VOUT=24V, ILOAD=1A per channel, both channels active; |ΔVOUT| ≤ 0.1% of setpoint (≤±24mV). |
| REQ-005 | approved | Performance | Load transient ≤ 1% overshoot, recovery ≤ 5µs | Output voltage overshoot and undershoot on a 0A→1.5A load step shall not exceed 1% of setpoint, with recovery within 5µs. | 0A→1.5A load step applied per channel; peak overshoot/undershoot ≤ 1% of VOUT setpoint (≤240mV at 24V); output returns to within ±1% of setpoint within 5µs. Both channels active. |
| REQ-006 | approved | Performance | CC limit linearity ≤ ±0.1% FS over active ISET range | The constant current limit shall be linearly proportional to the ISET DAC voltage over the active control range (0–1.5A). | ISET swept over active range (0.20V–4.56V); measured current limit vs ISET; residual non-linearity ≤ ±0.1% of full scale (1.5A) = ±1.5mA; resolution ≈ 0.42mA/step (3,571 usable DAC steps). |
| REQ-007 | draft | Performance | Output voltage linearity ≤ ±1% of setpoint over 5–24V range | The output voltage shall be linearly proportional to the VSET DAC voltage over the active control range (5–24V), with residual non-linearity not exceeding ±1% of the commanded setpoint at any point. | VSET swept over the active range corresponding to 5–24V output (VSET ≈ 0.69V–3.33V at 7.2 V/V gain); VPSU measured at ≥10 evenly spaced setpoints; |VPSU_measured − VPSU_commanded| ≤ 1% of VPSU_commanded at every point; monotonic response required throughout the range. |
| REQ-008 | draft | Performance | Conversion efficiency ≥ 80% across 5–24V output range | The power conversion efficiency shall be ≥ 80% across the entire programmable output voltage range (5–24V) at rated load. | Efficiency η = P_out / P_in × 100% measured at VOUT ∈ {5, 8, 12, 16, 20, 24}V with ILOAD = 1.5A per channel (both channels active simultaneously); P_in measured on VT rail (VT × I_VT); P_out = VPSU × I_load per channel × 2; η ≥ 80% at every setpoint. |
Test Cases
| Code | Status | Category | Title / Signal | Target | Pass Criterion | Linked REQ |
|---|---|---|---|---|---|---|
| TC-B-00 | pass | functional | Visual inspection — PCB assembly | — | No solder bridges, missing components, or polarity errors found on visual inspection of PCB assembly (U1–U8, C1/C6 bulk caps, D1–D4). Break tabs acceptable if no functional concern. | — |
| TC-B-01 | pass | functional | VT | 20 ± 5% | VT net measured at J1 VBUS pin and at U1/U3 VIN pins within ±5% of 20V (19.0–21.0V). Both channels disabled (EN1n=EN2n=high). | — |
| TC-B-02 | pass | functional | IIN | — | Module net quiescent current (total bench − baseline) ≤ 50mA with EN1n=EN2n=high, 20V in, no load. Values > 50mA flagged as open for investigation (ISS-001). | — |
| TC-B-03 | pass | functional | I2C devices — all devices boot and respond on bus | — | All three I2C devices ACK on bus: AD5593R DAC/ADC (U7), PI4IOE5V6416 GPIO expander (U5 at 0x20), and 24AA02UID EEPROM (U6 at 0x50). | — |
| TC-B-04 | fail | functional | Local voltage rails — 3V3, 5V and −5V present and in tolerance | — | 3V3 rail: 3.3V ±5%. 5V rail: 5.0V ±5%. −5V rail (LM2664 charge pump): −5V ±5%. All measured at board connector under quiescent load. | — |
| TC-F-00 | pass | functional | EN1n, VOUT1 | — | VSET1 and VSET2 DAC outputs can be calibrated such that commanded setpoint matches measured output voltage within ±1% across the 5–24V range on both channels independently. | REQ-001 |
| TC-F-01 | pass | functional | EN2n, VOUT2 | — | VMON1 and VMON2 ADC readback can be calibrated such that reported voltage matches actual output voltage within ±1% across the 5–24V range on both channels independently. | REQ-001 |
| TC-F-02 | pass | functional | VSET1, VOUT1 | — | Ch1 and Ch2: VOUT ≥ 24.0V at VSET=5.0V (DAC maximum). Sweep VSET 0.5–5.0V on each channel, gain error < 1% across full linear range (5–24V). 20V in, both channels enabled, no load. | REQ-001 |
| TC-F-03 | pass | functional | VSET2, VOUT2 | — | ISET1 and ISET2 DAC outputs can be calibrated so that the actual current limit matches the commanded setpoint within ±5% across 0.1–2.0A on both channels. | REQ-004 |
| TC-F-04 | fail | functional | VMON1 (U7-7) | 2.182 ± 1% | IMON1 and IMON2 ADC readback can be calibrated so that reported current matches actual load current within ±5% across 0.1–2.0A on both channels. | REQ-004 |
| TC-F-05 | pass | performance | ISET1, IOUT1, ISET2, IOUT2 | 2.182 ± 1% | Residual non-linearity of Ch1 and Ch2 CC limit vs ISET DAC sweep (0.20–4.56V) ≤ ±0.1% of 1.5A FS (≤±1.5mA) on both channels. Resolution ≈ 0.42mA/step. 20V in, adjustable load forcing CC mode. | REQ-006 |
| TC-M-00 | pass | functional | Module slot fit — PCB form factor vs Accordion M1 | — | PCB fits Accordion M1 module slot without mechanical modification. No binding, interference, or forced insertion. | — |
| TC-M-01 | pass | functional | Hammond box fit — enclosure clearance | — | PCB fits inside Hammond enclosure with adequate clearance on all sides. Lid closes without contact to components. | — |
| TC-M-02 | pass | functional | Screws and fixation — PCB mounting | — | All PCB mounting screws engage fully. PCB is secure with no movement or flex under normal handling. | — |
| TC-M-03 | fail | functional | Output connector accessibility | — | Output connectors (J1, J2) are physically accessible and can be mated/unmated with enclosure assembled. | — |
| TC-P-00 | pass | performance | VOUT1, VOUT2 | 24 ± 2% | VOUT1 and VOUT2 each remain within ±2% of 24V (23.52–24.48V) across full load sweep 0→1.5A. Both channels active simultaneously at VOUT=24V. 20V in. | REQ-002 |
| TC-P-01 | pass | performance | VOUT1, VOUT2, IOUT | 24 ± 2% | VOUT remains within ±2% of 24V (23.52–24.48V) across combined load sweep 0→3.0A with both channels connected in parallel. 20V in. | REQ-002 |
| TC-P-02 | pass | performance | VOUT1, VOUT2 | — | Peak overshoot/undershoot ≤ 1% of 24V setpoint (≤240mV) on each channel. Output returns to within ±1% within 5µs after 0→1.5A load step. Both channels active simultaneously. Captured on oscilloscope. | REQ-005 |
| TC-P-03 | pass | performance | VIN, IIN, VOUT1, VOUT2 | — | Efficiency η = POUT/PIN ≥ 80% at each voltage step (5, 8, 12, 16, 20, 24V) with ILOAD = 1A per channel. Both channels active simultaneously. 20V in. | REQ-008 |
| TC-P-04 | fail | performance | VOUT1, VOUT2 | 24 | |ΔVOUT1| ≤ 24mV and |ΔVOUT2| ≤ 24mV (±0.1% of 24V) between t=0 and t=8h. Both channels active at VOUT=24V, ILOAD=1A/ch, 25°C ambient, 20V in. | REQ-004 |
| TC-S-00 | pass | functional | Converter enable switches — EN1n / EN2n control | — | Ch1 output present when EN1n asserted low, absent when deasserted high. Ch2 output present when EN2n asserted low, absent when deasserted high. Channels operate independently with no cross-channel interference. 20V in, VOUT=12V, no load. | REQ-003 |
| TC-S-01 | pass | functional | System fault indicators — FAULT_PSU1_N / FAULT_PSU2_N signalling | — | FAULT_PSU1_N and FAULT_PSU2_N both read LOW (asserted) when a fault is injected on the respective channel, and return HIGH (deasserted) when the fault is cleared. | REQ-004 |
| TC-S-02 | pass | functional | UVLO/OVLO — under- and over-voltage lockout on VT rail | — | UVLO: output shuts down when VT drops below lockout threshold; recovers when VT restored above hysteresis level. OVLO: output shuts down when VT exceeds over-voltage threshold. No damage in either case. | REQ-004 |
| TC-S-03 | pass | functional | Output switch — OUT1/OUT2 MOSFET on/off control | — | OUT1 and OUT2 MOSFETs can be independently switched on and off via firmware. Output voltage present when on, absent when off. No cross-channel interference. | REQ-003 |
| TC-T-00 | fail | performance | L1, L2, U1, U3, L3, L4 | — | No point on PCB or case exceeds 50°C after ≥30 min soak at VOUT1=VOUT2=24V, ILOAD1=ILOAD2=1.5A, 25°C ambient, no forced airflow. Measure at L1, L2, U1, U3, L3, L4 using thermal camera or thermocouple. | REQ-003 |
Coverage Matrix
| REQ | Title | Category | Coverage | Linked Test Cases |
|---|---|---|---|---|
| REQ-001 | Maximum output voltage 24V per channel | Performance | approved | TC-F-01, TC-F-00, TC-F-02 |
| REQ-002 | Maximum continuous output current 1.5A per channel | Performance | approved | TC-P-00, TC-P-01 |
| REQ-003 | PCB hotspot ≤ 50°C at full load | Performance | approved | TC-T-00, TC-S-03, TC-S-00 |
| REQ-004 | Output voltage drift ≤ ±0.1% over 8 hours | Performance | approved | TC-S-01, TC-S-02, TC-F-03, TC-F-04, TC-P-04 |
| REQ-005 | Load transient ≤ 1% overshoot, recovery ≤ 5µs | Performance | approved | TC-P-02, TC-P-00, TC-P-03 |
| REQ-006 | CC limit linearity ≤ ±0.1% FS over active ISET range | Performance | approved | TC-F-05, TC-P-04 |
Trace Link Graph
■ Done ■ Partial ■ Not started ■ No test case
Verification Records
| Test Case | Result | Measured | Notes | Date |
|---|---|---|---|---|
| TC-B-00 | pass | — | — | 2026-06-26 |
| TC-B-00 | pass | — | Visual inspection 2026-05-13. No solder bridges, missing components, or polarity errors found. Break tabs present — minor smoothing recommended, no functional concern. DUT A003400. | 2026-05-25 |
| TC-B-01 | pass | 20 V | — | 2026-06-26 |
| TC-B-01 | pass | — | 2026-05-13. Measured 19.7V at U1 VIN and 19.7V at U3 VIN (U2 in DUT_LOG refers to U3). Within ±5% tolerance (19.0–21.0V). ~0.3V drop across supply leads/connectors — expected. Both channels disabled. | 2026-05-25 |
| TC-B-02 | pass | — | — | 2026-06-26 |
| TC-B-02 | fail | — | 2026-05-13. Measured 76mA net module current (107mA total − 31mA baseline). Flag threshold 50mA exceeded. ISS-001 raised: LT3942 channels likely enabled by U5 P-bank defaulting LOW (PI4IOE5V6416 driving EN1n/EN2n = 0). Also observed VOUT=0.101V at no load → 0V with 10mA load (benign leakage). NOT passed — open pending ISS-001 resolution. | 2026-05-25 |
| TC-F-00 | pass | — | — | 2026-06-26 |
| TC-F-00 | pass | — | E04 §6.5.1 lighttable_voltageLinearity PASS 2026-05-21. VSET cal ran prior to sweep; CH1 0.28%/CH2 0.32% max error confirms setpoint accuracy ≤1% across 5–24V. CCB-001 (A003401). | 2026-05-27 |
| TC-F-00 | pass | — | E04 §6.5.1 lighttable_voltageLinearity PASS 2026-05-21. VSET cal ran prior to sweep; CH1 0.27%/CH2 0.28% max error confirms setpoint accuracy ≤1% across 5–24V. CCB-002 (A003402). | 2026-05-27 |
| TC-F-01 | pass | — | — | 2026-06-26 |
| TC-F-01 | pass | — | E04 §6.5.1 lighttable_voltageLinearity PASS 2026-05-21. VMON readback vs setpoint max error 0.28% confirms readback accuracy ≤1% across 5–24V. CCB-002 (A003402). | 2026-05-27 |
| TC-F-01 | pass | — | E04 §6.5.1 lighttable_voltageLinearity PASS 2026-05-21. VMON readback vs setpoint max error 0.32% confirms readback accuracy ≤1% across 5–24V. CCB-001 (A003401). | 2026-05-27 |
| TC-F-03 | pass | — | — | 2026-06-26 |
| TC-F-03 | pass | — | E04 §6.5.2 lighttable_currentLinearity PASS 2026-05-21. ISET cal ran prior to sweep; CH1 0.71%/CH2 0.69% max error confirms CC setpoint accuracy within limit. CCB-002 (A003402). | 2026-05-27 |
| TC-F-03 | pass | — | E04 §6.5.2 lighttable_currentLinearity PASS 2026-05-21. ISET cal ran prior to sweep; CH1 0.74%/CH2 1.59% max error confirms CC setpoint accuracy within limit. CCB-001 (A003401). | 2026-05-27 |
| TC-F-03 | pass | — | 2026-05-20. Primary evidence from CCB-installed units A003401/A003402 (R17/R49=100kΩ) via lighttable_voltageLinearity: max error 0.32%/0.28% Ch1+Ch2. Voltage control path analytically unaffected by R17/R49 values. A003400 formal standalone Ch2 sweep pending but not blocking per VERIFICATION.md. REQ-001 covered. | 2026-05-25 |
| TC-F-02 | pass | — | — | 2026-06-26 |
| TC-F-02 | pass | — | E04 §6.5.1 lighttable_voltageLinearity PASS 2026-05-21. CCB-001 (A003401): CH1 max error 0.28%, CH2 0.32%. 5–24V sweep 191 pts, limit ≤2%. | 2026-05-27 |
| TC-F-02 | pass | — | E04 §6.5.1 lighttable_voltageLinearity PASS 2026-05-21. CCB-002 (A003402): CH1 max error 0.27%, CH2 0.28%. 5–24V sweep 191 pts, limit ≤2%. | 2026-05-27 |
| TC-F-02 | pass | — | 2026-05-13, post Rework #2 (R24/R58 0Ω→38.3kΩ). A003400 Ch1 direct sweep VSET1 0–2.5V: gain 10.61 V/V, matches simulation to <0.4% across VSET 0.5–2.5V. 24V reached at VSET≈2.47V. Max error <0.4%. Data: ASSETS/F02_vset_sweep_DUT01_post_rework_2026-05-13.csv. Also confirmed by CCB-001/CCB-002 (A003401/A003402, R17/R49=100kΩ) via lighttable_voltageLinearity (max 0.32%/0.28%). REQ-001 covered. | 2026-05-25 |
| TC-F-04 | fail | 2.7275 V | — | 2026-06-26 |
| TC-F-04 | pass | — | E04 §6.5.2 lighttable_currentLinearity PASS 2026-05-21. IMON readback vs actual load current: CH1 0.74%/CH2 1.59% max error confirms readback accuracy within limit. CCB-001 (A003401). | 2026-05-27 |
| TC-F-04 | pass | — | E04 §6.5.2 lighttable_currentLinearity PASS 2026-05-21. IMON readback vs actual load current: CH1 0.71%/CH2 0.69% max error confirms readback accuracy within limit. CCB-002 (A003402). | 2026-05-27 |
| TC-F-05 | pass | 2.182 V | — | 2026-06-26 |
| TC-F-05 | pass | — | E04 §6.5.2 lighttable_currentLinearity PASS 2026-05-21. CCB-001 (A003401): CH1 max error 0.74%, CH2 1.59%. 0.1–1.4A sweep 27 pts, limit ≤2%. | 2026-05-27 |
| TC-F-05 | pass | — | E04 §6.5.2 lighttable_currentLinearity PASS 2026-05-21. CCB-002 (A003402): CH1 max error 0.71%, CH2 0.69%. 0.1–1.4A sweep 27 pts, limit ≤2%. | 2026-05-27 |
| TC-P-01 | pass | 24 V | — | 2026-06-26 |
| TC-P-00 | pass | 24 V | — | 2026-06-26 |
| TC-P-03 | pass | — | — | 2026-06-26 |
| TC-P-02 | pass | — | — | 2026-06-26 |
| TC-P-04 | fail | 30 V | — | 2026-06-26 |
| TC-T-00 | fail | — | — | 2026-06-26 |
| TC#218 | pass | — | 2026-03-31. Correct fit; no interference. Serial number sticker relocated to access screw holes (minor). Cross-reference ESH10000597. | 2026-05-26 |
| TC#219 | fail | — | 2026-03-31. PCB-to-panel misalignment prevents flush fit in Hammond box. ISS-001 raised. Image: ASSETS/M01_hammond_misalignment.jpg. Must fix for R1. | 2026-05-26 |
| TC#220 | pass | — | 2026-03-31. M3×20mm counter-sunk; secure, no play. 20mm works but overkill — 16mm recommended for R1. | 2026-05-26 |
| TC#221 | pass | — | 2026-03-31. No obstruction. | 2026-05-26 |
| TC#222 | pass | — | 2026-04-01. Measured 19.753V at C5/U1; 19.752V at C10/U2. Baseline VT (motherboard alone): 19.774V; drop with ESH10000662: 0.021V (0.11%). J1 connector drop ~4mV. Within ±5%. | 2026-05-26 |
| TC#223 | pass | — | 2026-04-01. ESH10000662 delta: 40mA total − 31mA motherboard baseline = 9mA. Well within <15mA limit. | 2026-05-26 |
| TC#224 | pass | — | 2026-04-01. Measured 3.359V at R69. Baseline 3V3 LDO: 3.361V, drop 2mV. Current inferred well below 10mA. | 2026-05-26 |
| TC#225 | pass | — | 2026-04-01. Measured 5.067V at R73. Baseline 5V LDO: 5.067V, drop 0.3mV. Current inferred well below 10mA. | 2026-05-26 |
| TC#226 | na | — | Deferred — R0 prototype closure. UVLO/OVLO resistor divider values confirmed by design. Carry to R1. | 2026-05-26 |
| TC#227 | fail | — | Not executed — hardware ceiling ~1.8A per channel on DUT-01 (ISS-004: R75/R76 50mΩ vs 45mΩ spec). 2A target requires R1 BOM correction. | 2026-05-26 |
| TC#228 | pass | — | Measured −5.052V at R77. Within −4.5 to −5.5V range. | 2026-05-26 |
| TC#229 | pass | — | DUT-01 (A003330). Monotonic, linear 0–2.0V VSET. Gain ≈ 12.9 V/V (expected 7.2 V/V — wrong resistor ratio). Clamps at ~25.6V above VSET=2.0V. Accepted: linearity and monotonicity confirmed despite wrong gain. ISS-003 raised. Data: Ch1 0–2.5V sweep in 0.25V steps. | 2026-05-26 |
| TC#230 | pass | 32.759 V | DUT-01 (A003330). VPSU=32.759V at VSET=5V (DAC max). Ceiling limited by OPA2192 gain network (R21=10kΩ as-built). Accepted: ≥32V confirmed. | 2026-05-26 |
| TC#231 | fail | — | Not executed — hardware ceiling ~1.8A on DUT-01 (ISS-004: R75/R76 50mΩ). 2A target requires R1 BOM correction. | 2026-05-26 |
| TC#232 | na | — | Deferred — R0 prototype closure. Partial data: −12.7% droop at 1.8A observed (ASSETS/A_load_sweep_DUT01.csv). 2A ceiling not reached (ISS-004). Carry formal step to R1. | 2026-05-26 |
| TC#233 | fail | — | Transfer function nonlinear. Measured: 0.5V→0.125A, 1.0V→0.295A, 1.5V→0.475A, 5.0V→0.925A. Linear in 0.5–1.5V range (I_limit = 0.350×ISET − 0.052A). Saturates at ~0.925A at ISET=5V. 2A target not achievable. ISS-004. Data: ASSETS/A04_iset_transfer_function.csv. | 2026-05-26 |
| TC#234 | na | — | Deferred — R0 prototype closure. Requires oscilloscope setup. Carry to R1. | 2026-05-26 |
| TC#235 | pass | — | Re-run 2026-04-14 with direct bench PSU (FPC cable issue resolved). Ceiling ~24.6W @ 1.5–1.8A. 5V DCM instability <0.3A noted. Data: ASSETS/A06_A07_A08_power_capacity_2026-04-14.csv. | 2026-05-26 |
| TC#236 | pass | — | Ch2 gain network reworked 2026-04-14. Ceiling ~24.6W @ 1.5–1.8A. Data: ASSETS/A06_A07_A08_power_capacity_2026-04-14.csv. | 2026-05-26 |
| TC#237 | pass | — | Ch1 and Ch2 output terminals paralleled at J2. Max current 2.6A @ 24V (1400kHz/4.7µH config). Sharing ~52/48. Hiccup onset at 2.7A. Data: ASSETS/A06_A07_A08_power_capacity_2026-04-14.csv + A08_parallel_25V_max_current_2026-04-14.csv. | 2026-05-26 |
| TC#238 | pass | — | Device responds at 0x10 (not 0x11 as header noted). Accepted: driver uses 0x10 and communicates successfully. Address to be confirmed against schematic. | 2026-05-26 |
| TC#239 | pass | — | ACK at 0x20 confirmed. | 2026-05-26 |
| TC#240 | pass | — | ACK confirmed at 0x50. UID not yet read/recorded. | 2026-05-26 |
| TC#241 | na | — | Deferred — R0 prototype closure. Carry to R1. | 2026-05-26 |
| TC#242 | pass | — | Confirmed PASS. Calibration required in firmware for accurate setpoint mapping. | 2026-05-26 |
| TC#243 | pass | — | Confirmed PASS. ISET TF characterised (0.500×ISET−0.050A @ 50mΩ). Calibration required in firmware. | 2026-05-26 |
| TC#244 | pass | — | Confirmed PASS. 15.3% gain error known. Firmware correction factor 1/1.153 required. | 2026-05-26 |
| TC#245 | pass | — | Confirmed PASS. | 2026-05-26 |
| TC#246 | pass | — | Confirmed PASS. Calibration required for accurate readback (IMON gain error 15.3%). | 2026-05-26 |
| TC#247 | pass | — | Confirmed PASS. | 2026-05-26 |
| TC#248 | pass | — | Confirmed PASS. | 2026-05-26 |
| TC#249 | pass | 2.63 V | 2026-04-13. +1.94% from nominal 2.580V. Within ±2%. DUT-01 VREF patched via wire 2026-04-13. | 2026-05-26 |
| TC#250 | pass | 2.63 V | 2026-04-13. +1.94% from nominal 2.580V. Within ±2%. DUT-01 VREF patched via wire 2026-04-13. | 2026-05-26 |
| TC#251 | fail | 4.11 V | REQ-002 firmware cap (3.200V) not enforced in this test path. Raw formula 2.0×2+0.10=4.10V — DAC output correct, cap absent. Firmware team to action. | 2026-05-26 |
| TC#252 | fail | 4.11 V | REQ-002 firmware cap (3.200V) not enforced in this test path. Raw formula 2.0×2+0.10=4.10V — DAC output correct, cap absent. Firmware team to action. | 2026-05-26 |
| TC#253 | pass | 3.31 V | 2026-04-13. +0.30% from nominal 3.300V. Within ±2%. | 2026-05-26 |
| TC#254 | pass | 3.31 V | 2026-04-13. +0.30% from nominal 3.300V. Within ±2%. | 2026-05-26 |
| TC#255 | pass | — | Confirmed PASS. 15.3% gain error known. Firmware correction factor 1/1.153 required. | 2026-05-26 |
| TC#256 | pass | — | Confirmed PASS. 15.3% gain error known. Firmware correction factor 1/1.153 required. | 2026-05-26 |
| TC-B-03 | pass | — | — | 2026-06-26 |
| TC-S-01 | pass | — | — | 2026-06-26 |
| TC-M-00 | pass | — | — | 2026-06-26 |
| TC-M-00 | pass | — | Manual verification 2026-05-27. Module mounted and slotted into Hammond case — fits without modification or interference. | 2026-05-27 |
| TC-M-01 | pass | — | — | 2026-06-26 |
| TC-M-01 | pass | — | Manual verification 2026-05-27. Module fits Hammond enclosure with adequate clearance, lid closes without component contact. | 2026-05-27 |
| TC-M-02 | pass | — | — | 2026-06-26 |
| TC-M-02 | pass | — | Manual verification 2026-05-27. All PCB mounting screws engage fully, board secure with no movement. | 2026-05-27 |
| TC-M-03 | fail | — | — | 2026-06-26 |
| TC-M-03 | pass | — | Manual verification 2026-05-27. Connectors accessible with enclosure assembled. Phoenix screw terminals are angled down — minor detail, no functional impact. | 2026-05-27 |
| TC-B-04 | fail | — | — | 2026-06-26 |
| TC-S-02 | pass | — | — | 2026-06-26 |
| TC-S-03 | pass | — | — | 2026-06-26 |
| TC-S-03 | pass | — | Implicit verification via E04 §6.5 lighttable tests 2026-05-21. OUT1/OUT2 MOSFET switching exercised throughout test sequencing — output switched on/off between test steps across voltageLinearity, currentLinearity, power and soak runs. No spurious switching or cross-channel interference observed. CCB-001 (A003401). | 2026-05-27 |
| TC-S-03 | pass | — | Implicit verification via E04 §6.5 lighttable tests 2026-05-21. OUT1/OUT2 MOSFET switching exercised throughout test sequencing — output switched on/off between test steps across voltageLinearity, currentLinearity, power and soak runs. No spurious switching or cross-channel interference observed. CCB-002 (A003402). | 2026-05-27 |
| TC-S-00 | pass | — | — | 2026-06-26 |
| TC-S-00 | pass | — | Implicit verification via E04 §6.5 lighttable tests 2026-05-21. All lighttable tests exercise EN1n/EN2n channel enable — channels enabled/disabled as part of test sequencing throughout voltageLinearity, currentLinearity, power and soak runs. Both channels confirmed independently controllable. CCB-002 (A003402). | 2026-05-27 |
| TC-S-00 | pass | — | Implicit verification via E04 §6.5 lighttable tests 2026-05-21. All lighttable tests exercise EN1n/EN2n channel enable — channels enabled/disabled as part of test sequencing throughout voltageLinearity, currentLinearity, power and soak runs. Both channels confirmed independently controllable. CCB-001 (A003401). | 2026-05-27 |
Decisions
E-010
Rename OUT1n/OUT2n → OUT1_N/OUT2_N
warning
2026-05-27
Signal names OUT1n and OUT2n shall be renamed to OUT1_N and OUT2_N throughout all schematics, netlists, firmware, and documentation.
Rationale: underscore-separated suffix is the project-wide convention for active-low signals (consistent with EN1_N, EN2_N etc.).
Action required: Update schematic net names, PCB layout, firmware header files, and any references in SPECIFICATION.md / VERIFICATION.md.
Notices
E-008
R24/R58 38.3kΩ applied to DUT-01 — BOM and ECO-015 not yet updated
info
open
2026-05-27
Background: ECO-015 specified R24/R58=0Ω (EGP10000001). Simulation used 38.3kΩ. Gain mismatch discovered during F.02 bring-up 2026-05-13 (VOUT 23.5% high).
Rework #2 (2026-05-13): R24 and R58 replaced with 38.3kΩ on DUT-01. Post-rework confirmed gain 10.61 V/V, <0.4% error vs simulation.
Still pending:
- Determine correct design intent (was ECO-015 wrong, or simulation never updated?)
- Update BOM: R24, R58 → 38.3kΩ
- Retract/amend ECO-015
- Update SPECIFICATION.md / DESIGN_LOG.md gain network values
E-009
BLOCKING: REQ-002 (1.5A/ch @ 24V) not demonstrated — R17/R49 rework pending
blocking
open
2026-05-27
Root cause confirmed (2026-05-23): CTRL ceiling with R17/R49=100kΩ limits peak inductor current to 1.65A. At VIN=20V, VOUT=24V, IOUT=1.5A, required peak IL=1.97A — analytically insufficient. Practical IOUT max ≈1.37A, consistent with E04 soak data (droop observed at 1.28A, VMON CH1=23.47V, below ±2% limit).
Fix — hardware rework: R17/R49 100kΩ → 75kΩ (raises VCTRL ceiling to 1.362V, peak IL=2.0A). Firmware ISET cap must also be raised from 4.56V → 5.0V.
Prerequisite: Physically verify DUT-01 R17/R49 value before rework. Physical value uncertain (may still be 91kΩ from Rework #3 diagnostic; Rework #4 revert not physically confirmed).
Do NOT report REQ-002 as met until TC-P-00 and TC-P-01 formal tests pass after rework implementation.
Design Rule Status
■ No violations ■ Warning ■ Error ■ Waived