Mini-PSU

ESH10000662 · Rev R1

in_progresselectronics

2-channel programmable buck-boost PSU Comtop Module. LT3942-based converters, 20V input, 0–24V/1.5A per channel output, DAC-controlled (VSET/ISET via AD5593R). VMON1/VMON2 output monitoring, PWM1n/PWM2n GPIO outputs via PI4IOE5V6416 expander. R1 adds VMON monitoring (ECO-012/013) and PWM expander relocation (ECO-010/011).

Reports Audit Log

Everything here lives inside a Project (a code + revision, e.g. ESH10000540 R3). The backbone is the V-model, read top-to-bottom: define what the product must do, plan how to prove it, execute the proof on real units, then learn from the field — and the Loop closes back up to the top.
This map is live: a block is green with a count when this project actually has that entity, and dashed/dim when it’s empty. Click any block to open its tab; hover for details. Arrows are the meaningful links; the implicit “belongs to this Project” edge is left out for legibility.

What each thing means

Requirement: One thing the product must do or satisfy — the “what”.
Test Case: A defined check that proves one or more requirements — the “how we prove it”. A verified_by trace link ties a test case to the requirement(s) it covers; that link is exactly what Coverage % counts. (So: a test case refers to the requirements it verifies.)
Verification Plan: A named grouping of test cases, approved before a test campaign and optionally gated by a milestone.
Verification Record: The result of running one test case against one unit: pass / fail / error / na. This is the evidence a requirement is actually met.
DUT: Device Under Test — an individual physical unit (by serial number) that records and test data attach to.
Deviation: A documented waiver against a verification record (e.g. accept a known non-conformance, with justification).
Entry: A knowledge note: a decision (settled choice), notice (assumption / risk / open question), issue (tracked problem), or concept (idea under exploration). It can attach to any other entity.
Design Rule: A reusable, checkable engineering constraint. Running the checks turns each violation into a Conflict.
Conflict: An open flag raised by a failed design-rule check (or an end-of-life / component-library issue) that needs resolving.
Milestone: A dated gate; verification plans can be tied to it.
Field Issue (RMA): A failure reported from the field on a returned unit; Root-Cause Analysis explains why it happened.
The Loop (S-16): loop_trace reconciles a field issue against that unit’s own verification record (did it pass at the edge of the band?). closes_loop records the corrective decision or design rule so the lesson is captured — and clears the project’s open-loop count.
Interface / Port: A contract between projects; each port can be driven by a requirement (and cascade one into the connected project).
BOM Component: A part on this project’s bill of materials, optionally linked to the shared Component Library.
GRR Study: A Gauge R&R study measuring how repeatable a test case’s measurement is.
Test Data: Production / Maestro run results recorded against DUTs — the population behind a single verification record.

100% Coverage

50% Done

6 Requirements

25 Test Cases

1 Blockers

2 Open Entries

Relation	Project
Related to	ESH10000690 R0 — Mini-PSU Precision Module

Timeline

Color = derived gate state · hover a tile for its note.

overdue / blocked

🏁 Release

· 3/6

Status & gates

Chronological — Release is the final gate. Derived & read-only; edit via trace_milestone_* tools.

Release / Readiness overdue / blocked 3/6 met1 failing

pending Requirements approved

REQ-007: draft
REQ-008: draft

met Coverage ≥ 100%

6/6 requirements covered (100%)

failing All test cases pass

20/25 passed
5 failing: TC-F-04, TC-P-04, TC-M-03, TC-B-04, TC-T-00

pending No blocking issues open

E-009: open blocker

met Deviations resolved

met Interfaces frozen

Test Cases

20 Pass 5 Fail / Deviated 0 N/A 0 Open0 / 25 Maestro impl.

Coverage — 100.0% · Done — 50.0%

3 Done 3 Partial 0 Not Started 0 Missing 2 Draft 0 Obsolete

Code	Title	Category	Coverage	Status
`REQ-001`	Maximum output voltage 24V per channel	Performance	Covered	Done
`REQ-002`	Maximum continuous output current 1.5A per channel	Performance	Covered	Done
`REQ-003`	PCB hotspot ≤ 50°C at full load	Performance	Covered	Partial
`REQ-004`	Output voltage drift ≤ ±0.1% over 8 hours	Performance	Covered	Partial
`REQ-005`	Load transient ≤ 1% overshoot, recovery ≤ 5µs	Performance	Covered	Done
`REQ-006`	CC limit linearity ≤ ±0.1% FS over active ISET range	Performance	Covered	Partial
`REQ-007`	Output voltage linearity ≤ ±1% of setpoint over 5–24V range	Performance	—	—
`REQ-008`	Conversion efficiency ≥ 80% across 5–24V output range	Performance	—	—