Accordion M1
ESH10000597 · Rev R0
Accordion M1 main board — R0 prototype. USB-C PD 20V input, TPS259474 E-Fuse protection on 3 rails, regulated outputs 5V/12V/3.3V/2.5V/1.8V/2.5VREF. Module connectors: SO-DIMM (J9), M2 (J15), N-Top (J10/J11/J12), Comtop (J3). I2C bus mux (74CB3Q3251) Ch0–Ch7. ADC monitoring via AD5593R (U24). Fan control via MAX6650 (U21). LED driver LP5012. RTC PCF8523 (U32). T1DATA[0:95] bidirectional bus routing. Enclosure: Hammond box with front/back/top panels.
Everything here lives inside a Project (a code + revision, e.g. ESH10000540 R3).
The backbone is the V-model, read top-to-bottom: define what the product must do, plan how to prove it,
execute the proof on real units, then learn from the field — and the Loop closes back up to the top.
This map is live: a block is green with a count when this project actually has that entity,
and dashed/dim when it’s empty. Click any block to open its tab; hover for details.
Arrows are the meaningful links; the implicit “belongs to this Project” edge is left out for legibility.
What each thing means
- Requirement
- One thing the product must do or satisfy — the “what”.
- Test Case
- A defined check that proves one or more requirements — the “how we prove it”. A verified_by trace link ties a test case to the requirement(s) it covers; that link is exactly what Coverage % counts. (So: a test case refers to the requirements it verifies.)
- Verification Plan
- A named grouping of test cases, approved before a test campaign and optionally gated by a milestone.
- Verification Record
- The result of running one test case against one unit: pass / fail / error / na. This is the evidence a requirement is actually met.
- DUT
- Device Under Test — an individual physical unit (by serial number) that records and test data attach to.
- Deviation
- A documented waiver against a verification record (e.g. accept a known non-conformance, with justification).
- Entry
- A knowledge note: a decision (settled choice), notice (assumption / risk / open question), issue (tracked problem), or concept (idea under exploration). It can attach to any other entity.
- Design Rule
- A reusable, checkable engineering constraint. Running the checks turns each violation into a Conflict.
- Conflict
- An open flag raised by a failed design-rule check (or an end-of-life / component-library issue) that needs resolving.
- Milestone
- A dated gate; verification plans can be tied to it.
- Field Issue (RMA)
- A failure reported from the field on a returned unit; Root-Cause Analysis explains why it happened.
- The Loop (S-16)
loop_tracereconciles a field issue against that unit’s own verification record (did it pass at the edge of the band?).closes_looprecords the corrective decision or design rule so the lesson is captured — and clears the project’s open-loop count.- Interface / Port
- A contract between projects; each port can be driven by a requirement (and cascade one into the connected project).
- BOM Component
- A part on this project’s bill of materials, optionally linked to the shared Component Library.
- GRR Study
- A Gauge R&R study measuring how repeatable a test case’s measurement is.
- Test Data
- Production / Maestro run results recorded against DUTs — the population behind a single verification record.
Timeline
Color = derived gate state · hover a tile for its note.Status & gates
Chronological — Release is the final gate. Derived & read-only; edit viatrace_milestone_* tools.Release / Readiness overdue / blocked 3/6 met1 failing
pending Requirements approved
- No requirements in scope
pending Coverage ≥ 100%
- No requirements in scope
failing All test cases pass
- 33/40 passed
- 4 failing: TC-S-00, TC-M-08, TC-D-06, TC-S-01
- 3 not yet run
Test Cases
Coverage — 0.0% · Done — 0.0%
| Code | Title | Category | Coverage | Status |
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