Maestro
Live demo — data resets daily at 03:00 UTC. Nothing you enter is saved.

Accordion M1

ESH10000597 · Rev R0

in_progresselectronics

Accordion M1 main board — R0 prototype. USB-C PD 20V input, TPS259474 E-Fuse protection on 3 rails, regulated outputs 5V/12V/3.3V/2.5V/1.8V/2.5VREF. Module connectors: SO-DIMM (J9), M2 (J15), N-Top (J10/J11/J12), Comtop (J3). I2C bus mux (74CB3Q3251) Ch0–Ch7. ADC monitoring via AD5593R (U24). Fan control via MAX6650 (U21). LED driver LP5012. RTC PCF8523 (U32). T1DATA[0:95] bidirectional bus routing. Enclosure: Hammond box with front/back/top panels.

Reports Audit Log

Everything here lives inside a Project (a code + revision, e.g. ESH10000540 R3). The backbone is the V-model, read top-to-bottom: define what the product must do, plan how to prove it, execute the proof on real units, then learn from the field — and the Loop closes back up to the top.
This map is live: a block is green with a count when this project actually has that entity, and dashed/dim when it’s empty. Click any block to open its tab; hover for details. Arrows are the meaningful links; the implicit “belongs to this Project” edge is left out for legibility.

What each thing means

Requirement
One thing the product must do or satisfy — the “what”.
Test Case
A defined check that proves one or more requirements — the “how we prove it”. A verified_by trace link ties a test case to the requirement(s) it covers; that link is exactly what Coverage % counts. (So: a test case refers to the requirements it verifies.)
Verification Plan
A named grouping of test cases, approved before a test campaign and optionally gated by a milestone.
Verification Record
The result of running one test case against one unit: pass / fail / error / na. This is the evidence a requirement is actually met.
DUT
Device Under Test — an individual physical unit (by serial number) that records and test data attach to.
Deviation
A documented waiver against a verification record (e.g. accept a known non-conformance, with justification).
Entry
A knowledge note: a decision (settled choice), notice (assumption / risk / open question), issue (tracked problem), or concept (idea under exploration). It can attach to any other entity.
Design Rule
A reusable, checkable engineering constraint. Running the checks turns each violation into a Conflict.
Conflict
An open flag raised by a failed design-rule check (or an end-of-life / component-library issue) that needs resolving.
Milestone
A dated gate; verification plans can be tied to it.
Field Issue (RMA)
A failure reported from the field on a returned unit; Root-Cause Analysis explains why it happened.
The Loop (S-16)
loop_trace reconciles a field issue against that unit’s own verification record (did it pass at the edge of the band?). closes_loop records the corrective decision or design rule so the lesson is captured — and clears the project’s open-loop count.
Interface / Port
A contract between projects; each port can be driven by a requirement (and cascade one into the connected project).
BOM Component
A part on this project’s bill of materials, optionally linked to the shared Component Library.
GRR Study
A Gauge R&R study measuring how repeatable a test case’s measurement is.
Test Data
Production / Maestro run results recorded against DUTs — the population behind a single verification record.
0% Coverage
0% Done
0 Requirements
40 Test Cases
6 Open Entries

Timeline

Color = derived gate state · hover a tile for its note.
overdue / blocked
🏁 Release
· 3/6

Status & gates

Chronological — Release is the final gate. Derived & read-only; edit via trace_milestone_* tools.
Release / Readiness overdue / blocked 3/6 met1 failing
pending Requirements approved
  • No requirements in scope
pending Coverage ≥ 100%
  • No requirements in scope
failing All test cases pass
  • 33/40 passed
  • 4 failing: TC-S-00, TC-M-08, TC-D-06, TC-S-01
  • 3 not yet run
met No blocking issues open
met Deviations resolved
met Interfaces frozen
Attention 6 open entries

Test Cases

32 Pass 4 Fail / Deviated 1 N/A 3 Open0 / 40 Maestro impl.

Coverage — 0.0% · Done — 0.0%

0 Done 0 Partial 0 Not Started 0 Missing0 Obsolete
Entries
7 of 7
CodeKindTitleSeverityScopeStatusMilestoneCreated
E-001 notice ISS-001/002: All 3 E-Fuse OVLO dividers wrong — R14/R24/R64 DNP workaround, blocking for R1 warning record open — 2026-05-25
E-002 notice ISS-009: I2C Ch7 absent from FW after ISS-008 fix — SW follow-up pending info record open — 2026-05-25
E-003 notice ISS-011: PCF8523 (U32) removed as R0 workaround — RTC non-functional on DUT-01 info record open — 2026-05-25
E-004 notice ISS-010: U24 monitoring calibration error — S.00/S.01 fail; SW + R1 resistor fix needed warning record open — 2026-05-25
E-005 notice 19 open DL entries for R1 — 7 are Sev 4–5 critical changes warning record open — 2026-05-25
E-006 notice ISS-012: UART SO-DIMM fail — wrong GPIO routing (GPIO12/13 vs GPIO14/15), R1 layout fix required warning record open — 2026-05-25
E-007 decision I2C channels 5, 6, 7 verified by inference from channels 0–4 info record closed — 2026-05-26