Complete R1 pinout for M1 (44-pin RPi 4B header, PRT_16764). See E-018 for change rationale and review flags.

📝 UPDATE (2026-06-11) — JTAG no-swap, per [[E-033]]: pins 16/18 reverted to the old-product / R0 wiring — TDI=GPIO23 (pin 16), TMS=GPIO24 (pin 18). The Pi is a bit-bang JTAG master (no BCM2711 hardware-JTAG constraint) and the downstream slave is unchanged, so the proven order is retained.

📝 UPDATE (2026-06-16) — pins 1/17 corrected (E-050) and I2CSEL3/4 disposed (E-049): the original table copied pins 1 and 17 as "3V3 Power" from the standard RPi spec, but M1 does NOT consume Pi 3V3 there — M1 generates its own 3V3 via U8/U30 AMS1117. As-built: M1-1 carries RPI_ON to test point TP1 (high-Z monitor of the Pi's 3V3 output); M1-17 is no-connect. Schematic (done): M1-17 NC symbol added; M1-1 off-page RETAINED intentionally (RPI_ON/TP1 is a deliberate Pi-power monitor, see E-026) — Martin's "remove pin-1 off-page" is NOT applied. I2CSEL3 (pin 31) / I2CSEL4 (pin 33): required on those pins by the pinout spec; kept as named nets with explicit NC symbols (not routed to the muxes) — E-049.

Full Pinout

Summary

• 6 pins changed from R0 (✱): pins 8, 10, 11, 32, 33, 36
• 38 pins unchanged — includes JTAG pins 16/18, reverted to R0 per [[E-033]]
• UART pull-ups: TxD (8), RxD (10), RTS (11), CTS (36) — as-built uses 10kΩ (R15/R19/R24/R25); accepted per Martin schematic review 2026-06-16 (10k ratified)
• ⚠️ Pin 32 (GPIO12) SPI1_CS1_N: software GPIO CS only — hardware SPI1 CE1 unavailable (GPIO17 = RTS). Firmware review required.
• Pins 31 / 33 (I2CSEL3 / I2CSEL4): NC symbols added, names retained for pinout-spec traceability — E-049 resolved.
• Pins 1 / 17: pin 17 NC added; pin 1 RPI_ON/TP1 retained — E-050 resolved.

Open questions

• Firmware: confirm GPIO CS mode supported for SPI1_CS1_N on GPIO12
• JTAG: TMS/TDI order settled — no swap, TDI=GPIO23 / TMS=GPIO24, per [[E-033]]
• E-049 (CON-003): I2CSEL3 / I2CSEL4 — NC symbols added, names retained
• E-050 (CON-004): pin 17 NC added; pin 1 RPI_ON/TP1 retained (off-page NOT removed)

References

• E-017: original R0 pinout error analysis
• E-018: pinout change review notice
• E-033: JTAG no-swap decision (reverts pins 16/18)
• E-049 (CON-003): I2CSEL3 / I2CSEL4 disposition
• E-050 (CON-004): pin 1 / pin 17 disposition + this table update
• Source: reference_pinout.md + ESH10000597_R0_pinout_issues.md

Hypothesis

An on-board MCU (ESP32) could serve as a combined power-on controller and telemetry engine for Accordion M1 in a future revision — owning push-button power sequencing, the always-on housekeeping rail, and aggregation/reporting of the U24 ADC monitoring channels (rail voltages/currents, fan, etc.) over a digital interface, rather than relying on the 74HCS74 (U11) hardware latch + RPi-host polling used in R1.

This is recorded as a future tech study, not a committed change. It does not affect R1.

Context / why deferred

Per decision [[E-012]] the push-button / power-on MCU (ESP32 or ATtiny 3227) was rejected for R1 because:

• it adds an MCU programming step in assembly,
• it needs a 3V3 rail independent of power state (currently the 7805, see [[E-015]]),
• the prime customer runs always-on with no push-button need.

The power-latch path (U11) + 7805 always-on rail was retained for R1 instead. The feature was explicitly not ruled out for future revisions — this entry captures that follow-up.

Alternatives considered

• ESP32 — most capable (WiFi/BT, ample telemetry headroom) but heaviest firmware/programming burden.
• ATtiny 3227 — lighter weight, but still adds an assembly programming step and the independent rail requirement.
• Status quo (R1) — hardware latch + host-side telemetry; zero firmware burden, no power-on intelligence or autonomous telemetry.

Open questions

• Scope of telemetry the MCU should own vs. the RPi host (does it replace U24 host polling, or sit alongside it?).
• Independent housekeeping rail strategy — reuse 7805 vs. dedicated regulator.
• Manufacturing impact of the in-line programming step (cost, test fixture, provisioning).
• Whether this belongs in a future Accordion M1 revision or a new product platform.

Next step

Spin up a dedicated tech-study project/spike when prioritised; evaluate ESP32 vs ATtiny against telemetry scope, power-state independence, and assembly cost. No R1 action.

Problem

BOM line for U3 (ECS-3225MV oscillator) assigns EGP10000946, but SharpMES confirms EGP10000946 = ADS7828EB/2K5 (the ADC at U24).

• U3: ECS-3225MV → should be EGP10001799 (ECS-3225MV-200-BN-TR3)
• U24: ADS7828IPW → EGP10000946 ✓ (correct)

Impact

If BOM is submitted as-is, U3 position will be ordered/placed with ADS7828 ADC instead of the 20 MHz oscillator. Board will not function.

Required fix

Update BOM: U3 EGP → EGP10001799.

Independent audit of every one of the 87 post-layout warnings on board 7 (Accordion M1 R1), re-checked against the ODB netlist + datasheets rather than trusting the E-054 dispositions. Result: the dispositions hold for 86 of 87 — but E-054's blanket "SinglePointNet x61 -> TRIAGED, no defects" is NOT correct: there is one real defect (U7.1), and several pins E-054 never enumerated (U6.1, U7.1/.6, U12.20, U17.11/.16) — all benign on inspection EXCEPT U7.1.

1. I2cPullupMissing x16 — FALSE POSITIVE (confirmed)

All 16 lines (SCL0-7/SDA0-7) pulled to 3V3 via resistor arrays R3/R4/R5/R6 (EXB-N8V103JX). Verified pin-by-pin. Rule only matches 2-pin discrete pull-ups and misses array packages -> system bug raised as Probe BUG-011.

2. BomLayoutMismatch x10

• J9 (SO-DIMM): REAL. Connected refdes silently dropped from the BOM export by "Part List Exclude: True". ACTION: add J9 to BOM. (Already the one open action from E-054.)
• NRD0-8 (9): benign — they sit on NO net (electrically inert); a BOM-completeness curiosity only. Identity still unexplained.

3. SinglePointNet x61

35 connector/header pins (J6, J9, J10, J13, J15, J4, M1.17/31/33, S2.4/5/6, D3.5) — benign by nature (unused connector I/O; named ones dispositioned in E-041/049/050/051).

26 IC pins — verified individually:

• BENIGN (datasheet/topology-verified): U14.1/.5 (TMP236 NC, labeled); U6.1 (74LVC1G14 single-inverter spare pin); U11.5/.6/.9 (74HCS74 unused-FF OUTPUTS — its inputs ARE tied); U21.6/.7 (MAX6650 GPIO0/1, X-marked NC); U19.5 (24AA02 NC); U4.6/U5.6 (CB3Q3251 mux NC); U17.7/.23 (LM76005 NC — datasheet says leave floating); U17.11 (LM76005 SS/TRK — datasheet: leave floating for internal soft-start); U17.16 (LM76005 PGOOD open-drain, no consumer); U12.13 (TPS2373 PG open-drain); U12.16 (TPS2373 UVLO_SEL input, internal pull-up, float OK); U12.17/.18/.19 (TPS2373 TPL/TPH/BT open-drain outputs); U12.20 (TPS2373 NC, "leave open"); U10.3 (TPS259474 PG open-drain); U2.5 (TPS54302 EN floats-to-enabled, engineer-confirmed); U7.6 (74LVC2G17 unused output 1Y).
• COULD NOT DATASHEET-VERIFY: U27.10 (CH224Q) — disposition "open-drain" is plausible but the CH224Q datasheet is not in Probe (it was in mpn_unresolved). Supply a datasheet URL to confirm.
• REAL DEFECT: U7.1 — see below.

REAL DEFECT — U7.1 floating Schmitt-trigger input

U7 = 74LVC2G17 (dual non-inverting Schmitt buffer). Only one channel is used: 2A(pin3) <- oscillator U3 (ECS-3225MV), 2Y(pin4) -> R82 -> CLK0P. The SECOND buffer is unused, and its DATA INPUT 1A (pin1) = net (Net0)-275 is left FLOATING (datasheet-confirmed pin1 = data input). U6 (74LVC1G14) inverts the same clock to CLK0N. Floating CMOS inputs draw shoot-through current and can self-oscillate; standard practice is to tie unused gate inputs to a rail. Contrast U11 (74HCS74), whose unused flip-flop has its inputs tied — that one is correctly handled, which is why it is benign and U7 is not. FIX: tie U7.1 (1A) to GND or 1V8. (U7.6 / 1Y is an open output — harmless.) Severity: warning (board functions; this is a reliability/EMI cleanliness fix for the next layout pass).

Follow-ups

• Raise a Probe concern on U7.1 so the fix federates and gates Green (not yet done).
• Supply a CH224Q datasheet URL to close the one unverifiable pin (U27.10).
• E-054 to be amended: its "SinglePointNet -> no defects" line is superseded by this U7.1 finding.

— Verification performed against board 7 ODB netlist + acquired datasheets (74LVC2G17, LM76005RNPR, TPS2373-4RGWR).

Problem

D3 (SRV05-4, EGP10001794) pin 5 = VRAIL is unconnected. Confirmed in netlist (unconnected pin section, no "by TERM") and schematic page 9.

SRV05-4 SOT-23-6 pinout as used:

• Pin 1 = IO1 → CC1 ✓
• Pin 2 = GND ✓
• Pin 3 = IO2 → CC2 ✓
• Pin 4 = IO3 → USBDM ✓
• Pin 5 = VRAIL → FLOATING ✗
• Pin 6 = IO4 → USBDP ✓

Impact

Without VRAIL tied to a reference rail, the ESD clamp cannot properly clamp transients on CC1, CC2, USBDM, USBDP. USB-C ESD protection is non-functional.

Required fix

Connect D3-5 (VRAIL) to 3V3. Add 100n bypass cap between VRAIL and GND per datasheet.

Decision

Keep PoE as an input power source on Accordion M1 R1. Implement active PoE (IEEE 802.3at, 45W) via an on-board PD controller IC (TPS2373-4RGWR).

Rationale

• Active over passive: Passive PoE is not considered attractive enough on the current market to justify the design effort. Active (802.3at) is the standard expected by infrastructure and end users.
• 45W throttle: High-power PoE supply scenarios are not anticipated for M1 use cases. 45W (802.3at Type 2) is sufficient for the expected load profile.
• Component choice (TPS2373-4RGWR): The design already requires an external buck converter (LM76005) to handle the external PSU input via Phoenix connector. Reusing the same LM76005 for PoE input means the PD controller only needs to provide the 802.3at interface — no integrated DC-DC required. TPS2373-4RGWR is a pure PD interface IC with an integrated 100V FET, minimal external components, and supports up to 90W (headroom above the 45W operating point).

Rejected alternatives

• Passive PoE: Not attractive enough on the market for the effort. No negotiation, no standards compliance, requires custom injector ecosystem.
• 90W (802.3bt): Not required for current use cases, but the selected component (TPS2373-4) supports 90W — this should be investigated if higher-power PoE scenarios emerge.
• Integrated PD + DC-DC (e.g. TPS23730, LT4275A): Unnecessary — LM76005 already handles step-down for the external PSU path.

Follow-up

• Update REQ-014 to reflect active PoE 802.3at, 45W, TPS2373-4RGWR.
• Add TPS2373-4RGWR (EGP10001943) to BOM.
• Investigate 90W (802.3bt) headroom if high-power PoE use case is identified.

Decision

Select TPS2373-4RGWR (Texas Instruments, EGP10001943) as the PoE PD controller for Accordion M1 R1.

Rationale

• The design requires an external buck converter (LM76005) to handle the external PSU input via Phoenix connector. This same converter handles the PoE rail step-down (48V → 20V bus), meaning the PD controller only needs to provide the 802.3at interface — no integrated DC-DC required.
• TPS2373-4RGWR is a pure PD interface IC: handles 802.3at detection, classification, inrush limiting, MPS, and overcurrent/overvoltage protection only.
• Integrated 100V N-channel FET — no external FET needed.
• Minimal external component count.
• Supports up to 90W — operating at 45W leaves significant headroom. 90W operation should be investigated if high-power PoE use cases are identified.
• Competitive unit price (~31.62 kr).
• Package: VQFN-20 (5×5 mm).

Architecture

PoE RJ45 → Magnetics → TPS2373-4RGWR → LM76005 → 20V bus
Phoenix connector → (protection) → LM76005 → 20V bus

Rejected alternatives

• TPS23730: integrated DC-DC — unnecessary given LM76005 is already in the design.
• LT4275A: integrated synchronous flyback — same reason.
• AG9805M (Silvertel module): larger footprint, higher cost.

Component library

• PLEASE component ID: 3469
• SharpMES: EGP10001943
• Datasheet: TPS2373 SLVSE09D (TI)

Decision

Do not implement a push button / power-on MCU (ESP32 or ATtiny 3227) in Accordion M1 R1.

Rationale

• Manufacturing complexity: requires an MCU programming step during board assembly, adding cost and process overhead not justified at this stage.
• Independent 3V3 rail required: the MCU would need a 3V3 supply independent of power state. This is currently handled by a 7805 — which has a suspected footprint/part inconsistency that must be verified (see E-012).
• No market pull: the prime customer operates in always-on mode and has no interest in a push button. Always-on is already supported without MCU involvement.
• Complexity not warranted: the level of design and validation effort is not justified by current market or user cases.

Rejected alternatives

• ESP32: more capable but even heavier programming/firmware burden.
• ATtiny 3227: lighter, but still adds assembly step and independent power rail requirement.

Future

This feature is not ruled out for future revisions or new products. Adding it later would not conflict with existing units in the field.

Impact

• REQ-018 remains withdrawn.
• Always-on power behaviour (existing) is the supported path for R1.

⚠️ AMENDED by [[E-025]] (2026-06-11): the rail is no longer removed — it is repurposed to carry 20V (VIN). The 12V generation (buck stage) is still removed, but the rail net/connector pins are retained and tied to the 20V bus. Read this entry together with E-025 for the current position.

Decision

Remove the 12V rail from Accordion M1 R1.

Rationale

• No current N-Top or Comtop modules in the Accordion M1 product lineup require 12V.
• The one known case where 12V was exposed (6×IDC N-Top module, single project) can be served by mounting a Mini-PSU (Comtop module), which generates configurable output from the 20V bus.
• If a future module requires 12V, it can generate it locally on the module from the 20V main bus — this does not tamper with module interface requirements.
• Removal simplifies the design, reduces BOM complexity, and reduces test scope.

Rejected alternatives

• Keep 12V rail: no justified demand in current product roadmap. Adds a buck converter stage with no active consumer.

Impact

• REQ-013 remains withdrawn.
• MON_12V monitoring channel (referenced in REQ-040 and REQ-042) is now redundant — these requirements should be reviewed and updated to remove 12V references.
• 20V main bus remains available as the high-voltage source for any module needing to generate its own 12V.

Decision

Retain the 7805 linear regulator in Accordion M1 R1.

Rationale

The 74HCS74-based power latch (U11) requires an always-on 5V supply (VCC) to hold flip-flop state and enable push-button power control. The 7805 is the intended supply for this always-on rail — it must remain regardless of the MCU decision.

The push button / power-on MCU was rejected (E-012), but the latch-based power circuit using U11 is retained for R1. The 7805 is its dedicated supply.

Rejected alternatives

• Remove 7805: not possible — U11 power latch loses its supply rail and power button becomes non-functional.

Impact

• 7805 must not be removed from R1 schematic or BOM.
• Footprint/part confirmed SOT-89 (LCSC C347258) — see E-013 (resolved).

Correction 2026-06-15

Earlier wording described this as the always-on "3V3" supply. That was incorrect: the part is a 7805 and the rail is VCC = 5V (the 74HCS74 is a 5V logic device). A 3.3V output would have dissipated more across the linear regulator, not less. Thermal disposition captured in [[E-045]].

Decision

Route 5V to RPi via a fuse in parallel with R147. Q8 and all associated passives removed.

Rationale

Parallel fuse + R147 gives two simple mounting solutions on the finished device:

• Fuse mounted, R147 NM: protected 5V path with overcurrent fuse.
• R147 mounted, fuse NM: direct 5V path, simpler assembly, no fuse.

Both options are supported by the same PCB footprint with no rework or design change between variants.

Fuse specification

• Rating: 2A
• Part: TBD — to be confirmed with final BOM.

Deviation from DL-020

DL-020 specified R147 alone as sufficient. This implementation retains R147 but adds a parallel fuse footprint for the protected variant.

Impact

• Q8 circuit removed as planned.
• BOM has two DNP options depending on assembly variant — document in assembly instructions.
• REQ-011 (5V to RPi) is satisfied by both variants.

Decision

Replace original bulk capacitors (TDK CKG57NX7S2A226M500JH, EGP10001337) on VBUS and VPOE with 1× Samsung CL32Y106KCV6PNE per position.

Rationale

• Original part (CKG57NX7S2A226M500JH) is a double-stacked capacitor (5.0mm height) — not mountable by the fabricator (REQ-015 violation).
• Single 10µF/100V X7S 1210 MLCC is fab-compatible and sufficient for bulk decoupling at these rail positions.

Rejected alternatives

• 2× 1210 per position: more capacitance but unnecessary; adds BOM complexity and PCB area.
• 22µF/100V single MLCC: not available in fab-friendly height on LCSC.

Impact

• VBUS bulk cap: 1× EGP10001944
• VPOE bulk cap: 1× EGP10001944

Decision

The rail previously slated for removal as the "12V rail" in [[E-014]] shall not be removed. Instead, that rail (its net, distribution copper, and module-connector pins) shall be repurposed to carry 20V (VIN / main bus).

This amends [[E-014]]: the 12V generation stage (buck converter producing 12V) is still removed — no 12V is produced on the board — but the physical rail/pins are retained and tied to the 20V VIN bus rather than being depopulated.

Rationale

• Keeps the rail/connector pins useful: modules get a direct 20V VIN feed on those pins instead of a dead/removed net.
• Directly realises E-014's intent ("any module needing 12V can generate it locally from the 20V bus") — those pins now are 20V.
• Avoids removing copper/pins that may be reused.

Impact

• ⚠️ Module interface contract change: connector pins formerly designated 12V now carry 20V. Every mating module must be reviewed — anything that previously assumed 12V on those pins would now see 20V.
• REQ-013 (12V rail) is withdrawn. Decide whether the 20V distribution needs its own requirement or is covered by [[REQ-001]].
• Monitoring: confirm the 20V feed is covered by MON_VIN / MON_VBUS; note [[REQ-041]] still lists MON_C12V — fold this cleanup in.

R1 schematic check (2026-06-15, E-044 walk)

On-board side CONFIRMED: module-connector power pins are labelled VDD (= eFused ~20V VIN), not 12V — J10 (N-Top), J3 (Comtop), J15 (M2 slot); no 12V pin exists.

Disposition 2026-06-16 (engineer)

For the use cases we have so far, swapping those pins from 12V to 20V is not an issue — no current/known mating module is mis-fed by 20V on the VDD pins. The full cross-module audit (every possible N-Top/Comtop/M2 module) is a large, ongoing task that lives with each module's own design, not the M1 board. M1's obligation (rename/retie to 20V, document the contract change) is met. Remaining as a forward watch: whenever a new module is designed/mated, verify it expects 20V on the VDD pins. Severity downgraded — immediate concern cleared.

Decision

Use 1× EGP10001944 (Samsung CL32Y106KCV6PNE, 10µF/100V/X7S/1210) as CIN on LM76005 (PVIN pin).

Rationale

• TI datasheet (SNVSBK5A, Section 8.2.2.4) recommends 10µF–22µF ceramic for CIN, with voltage rating ≥ 2× VIN_max.
• Footprint allows only a single 1210 cap position — 2× parallel not possible.
• 10µF is at the lower bound of TI's recommended range but within spec.
• Voltage margin: 100V ÷ 57V (VPOE max) = 1.75× — slightly below TI's preferred 2× but acceptable for X7S dielectric.
• Same part as VBUS/VPOE bulk caps (E-021) — keeps BOM simple.

Rejected alternative

• 2× EGP10001944 (20µF): preferred electrically but not possible — only one 1210 footprint position available at LM76005 CIN.

Risk / layout note

• Per LM76005 datasheet Section 9: if LM76005 is located >5cm from input source, a 47–100µF electrolytic in parallel is recommended to damp input inductance ringing.
• Evaluate placement distance during layout. If distance exceeds ~5cm, add electrolytic bulk cap.

Decision

Use 62Ω (E24, 0402, ±1%) for CLSA resistor on TPS2373-4RGWR instead of the datasheet-nominal 63.4Ω (E96).

Rationale

63.4Ω is an E96 value not in stock and not immediately available on LCSC. 62Ω is a standard E24 value. The TPS2373 CLSA pin sources ~2.5V across the resistor; the resulting current must fall within the IEEE 802.3 Class 4 window (36.5–44mA). At 62Ω: I = 2.5V/62Ω = 40.3mA — comfortably within the window.

Rejected alternatives

• 68Ω: Marginal at minimum V_CLS — risk of falling below Class 4 floor. Rejected.
• 63.4Ω: Not in stock, no E24 equivalent. Not selected.

Follow-up

None required. Tolerance analysis confirms 62Ω safe across full V_CLS range.

Decision

Use 91Ω (E24, 0402, ±1%) for CLSB resistor on TPS2373-4RGWR. The datasheet-nominal value is 90.9Ω (E96).

Rationale

91Ω is a standard E24 value; difference from 90.9Ω is <0.1%, well within the ±1% resistor tolerance. The resulting classification current (2.5V/91Ω = 27.5mA) falls within the IEEE 802.3 Class 3 window (25.5–30.5mA). Values are functionally interchangeable.

Rejected alternatives

• 90.9Ω (E96): Not in stock. No practical benefit over 91Ω.

Follow-up

None required.

Decision

Connect AMPS_CTL to VSS via 1kΩ 0603 ±1% resistor to enable auto-MPS on TPS2373-4RGWR.

Rationale

Auto-MPS disabled (open) is fragile: if load drops below 10mA (bare board bring-up, RPi hot-removed, or future deep-sleep firmware), PSE cuts PoE port after ~400ms. 1kΩ adds I_pulse = 24V/1kΩ = 24mA peak, 3mA average at 12.5% duty cycle — supplements natural load current. Power dissipation = 72mW (within 0603 100mW rating). Simple, low-cost insurance.

Rejected alternatives

• Leave open: simpler but fragile under low-load scenarios.
• 300Ω: standalone 10mA compliance but requires 0805 ¼W package — unnecessary given M1 always draws significant current.
• 560Ω: 5.4mA average, 0805 ⅛W — overkill for supplemental use.

Follow-up

None required.

Decision

JTAG TMS/TDI shall NOT be swapped in R1. Retain the old-product / R0 wiring:

This reverts the TMS/TDI swap introduced for R1 in [[E-018]] / [[E-019]] (which had TMS=GPIO23/pin16, TDI=GPIO24/pin18).

Rationale

• No hardware constraint. The Pi is the JTAG master, driving a slave device on the modules. The BCM2711 has no JTAG-master peripheral — the ALT4 "JTAG" pins are the Pi's own ARM debug slave TAP (wrong signal directions, cannot master a downstream chain). Mastering is software bit-bang (e.g. OpenOCD bcm2835gpio), so the Pi imposes nothing on pin order or placement.
• Slave unchanged (confirmed). The downstream JTAG slave is unchanged from the old product and expects TDI=GPIO23 / TMS=GPIO24. Keeping this order preserves continuity with the proven, working old-product/R0 bring-up and toolchain (OpenOCD GPIO map) with no re-validation.
• No defect drove the swap. There is no recorded R0 JTAG test failure and no DESIGN_LOG item requesting a swap. The swap in E-017/E-018 originated only from diffing R0 against the ESH10000539 R1 (cm32) reference and assuming it authoritative — but cm32 is not this product's slave, so it is not a requirement here.

Rejected alternative

• Adopt the cm32 swap (TMS=GPIO23, TDI=GPIO24): rejected. Breaks continuity with the unchanged slave and proven old-product/R0 wiring for no benefit; any adaptation could be handled in the OpenOCD config regardless.

Impact

• Schematic: revert pins 16/18 to TDI=GPIO23, TMS=GPIO24 before tape-out (MS-001, 2026-06-15). TDO=GPIO22 and TCK=GPIO25 are unchanged.
• Supersedes the JTAG portion of [[E-017]] / [[E-018]] / [[E-019]]. E-019's full-pinout table (pins 16/18) to be updated to match.
• Other pins still under the E-017/E-018 review (UART, etc.) are not affected by this decision and remain open.

Note

Speed is not a function of JTAG pin placement here (bit-bang master). If higher JTAG throughput is ever needed, the lever is SPI-assisted JTAG (TCK←SCLK, data←MOSI/MISO, TMS←GPIO), not the ALT4 block — tracked separately if pursued.

Decision

LM76005RNPR (EGP10001802) configured as follows for the 20V bus:

Rationale

• VOUT 20.96V: Closest achievable with E24 resistors to 20V target. After E-Fuse forward drop the rail settles near 20.5V in practice. Acceptable.
• R_top as 2×100k series: R_top is implemented as two 100kΩ (R75 + R56) in series rather than a single 200kΩ — electrically identical (200kΩ total, same ratio), and avoids sourcing a separate 200kΩ part. This is the as-built schematic/BOM.
• Inductor: SRP7028AA-100M Irms=4A, Isat=5.5A. Peak inductor current at 4A load/400kHz/57V_max = 4.83A — within Isat with margin.
• RT floating: TI datasheet confirms 400kHz default when RT is not connected. 100kΩ DNP footprint added for future frequency tuning without schematic change.

Rejected alternatives

• Trimming feedback resistors to exact 20V: not achievable with E24-only constraint.
• RT resistor populated: not required for R1; left as DNP option.
• Single 200kΩ R_top: equivalent, but 2×100k retained as built (no 200kΩ part to source).

Follow-up

None required for R1.

Correction 2026-06-15

R_top value corrected from "1×200kΩ (EGP10000128)" to the as-built "2×100kΩ in series, R75+R56 (EGP10000121 ×2)" per E-044 colleague review. Electrically identical; engineer confirmed keeping 2×100k.

Accordion M1 R1 PCBA ordered at JLCPCB (qty 5) on 2026-06-17. Final upload BOM ESH10000597_BOM_JLCPCB.csv — 83 rows / 226 designators / 79 LCSC-assigned; 4 manual-or-DNP (B1, D14/D15, J8, S2).

Three near-misses caught during BOM prep (next-build checklist)

1. JLCPCB did not expand hyphen designator ranges — first upload silently dropped 62 components (every Cx-Cy/Rx-Ry/Dx-Dy/Qx-Qy/Jx-Jy range). Rule: always expand ranges to comma format before upload.
2. R40 (124 Ω) auto-matched to 120 kΩ (FRC0402F1203TS) — corrected to 124 Ω (C2974005).
3. 100 nF decoupling auto-matched to 16 V (C1525) but C11 on VDD (~20 V), C12 on VIN (~20 V), C20/21/56/63/68 on LM76005 ~21 V output → overvoltage. Original spec 50 V. Fixed: whole 100n group → C307331 (Samsung CL05B104KB54PNE, 100 nF 0402 50 V X7R).

Sourcing final state

Resolved via JLC matching: U4/U5 C2869261, U10/U16 C2864845, U11 C2866652, J4 C591322, J13 C3197888, AMS1117 C347224, SRP7028AA C3223565, M1 C22194615, J16 C3585882, F1 C70158, C60-62 C2167787. Hand-mount/consign: D14/D15 CD-MB210S (bridge), S2 PBH2UOANAHX (pushbutton). NM (not placed): B1, J8.

U24 grade

BOM ADS7828IPW (I) accepted as E-grade ADS7828E/2K5 (C701649) — TI only makes E (±1 LSB) and EB (±0.5 LSB), both −40…+85 °C; no real "I" grade; E fine for rail monitoring.

Re-created after the 2026-06-17 Trace server crash wiped that day's updates. Source: DOCS/ESH10000597_R1_TRACE_RECOVERY_2026-06-17.md.

Requirement REQ-014 ("PoE Input — Active 802.3at (45W)") has no verifying test case. Add one with please_testcase_create and link it (verified_by).

PoE input strategy for R1 is undecided.

Open question: Keep or remove PoE? If kept — active or passive? 45W or 90W?

See DL-023. Originally tracked as REQ-014.

Push button / power-on management by MCU is undecided.

Open question: ESP32 or ATtiny 3227? Define scope of MCU functions.

See DL-025. Originally tracked as REQ-018.

MCU signal routing to module slots is undecided.

Open question: Which slots? Which signal types?

See DL-026. Originally tracked as REQ-039.

12V rail inclusion for R1 is undecided.

Open question: Include or remove the 12V rail?

See DL-022. Originally tracked as REQ-013.

Implementation detail for REQ-011 (5V Supply to RPI).

• Q8 and associated components shall be absent from schematic and BOM
• 5V routed to RPi via R147

Implementation detail for REQ-004 (20V Supply Current Limit Protection).

• Current limit (ILIM) set to 5A via R39 = 680Ω

Implementation detail for REQ-005 (20V Supply Current Ramp).

• R1/R19/R63 = 0Ω (ramp resistors strapped)
• C24/C46/C51 = 330pF (ramp capacitors)

Applies to all E-Fuses.

M3×16mm screws for N-Top fixation have been found to cause collisions and need to be evaluated before prototype order.

Alternative screw lengths should be assessed against the PCB stackup and clearance zones.

The 7805 linear regulator (used to generate a 3V3 rail independent of power state) is suspected to have a footprint or part inconsistency in the current design.

This must be verified before layout sign-off to avoid a board spin caused by a wrong footprint or incompatible part selection.

Full comparison of ESH10000597 R0 M1 connector vs ESH10000539 R1 reference (cm32_r1.pdf, Sheet 3) reveals 12 functional errors. DL-017 only captured the UART routing issue — the full scope is:

Net names are correct for the design convention (TxD/RxD/RTS/CTS, not the reference's TxD1/RxD1 etc.). The errors are purely wrong GPIO-to-signal mappings.

Confirmed correct as-is:

• Pin 7 (GPIO4): SRQ_N (active-low) is correct — reference SYSTEM_SRQ naming not adopted.
• Pin 42: NC is correct — reference 5V assignment not applicable to this design.

All 12 corrections are captured in PLAN-SCH-001 Group 5. Source documents: reference_pinout.md and ESH10000597_R0_pinout_issues.md (Please/ESH10000671_R0/DOCS/).

The M1 connector (44-pin RPi header) has been substantially reworked in R1 vs R0. All 8 signal reassignments must be reviewed and verified before tape-out sign-off.

Changes (8 pins)

Confirmed unchanged (diverging from ESH10000539 R1 reference — intentional)

• Pin 13 (GPIO27): GPDAT0 retained
• Pin 27 (GPIO0): I2CSEL1 retained
• Pin 29 (GPIO5): I2CSEL2 retained
• Pin 31 (GPIO6): I2CSEL3 retained
• Pin 37 (GPIO26): GPDAT1 retained

Key review points

1. SPI1_CS1_N on GPIO12 (pin 32) — hardware SPI1 CE1 is unavailable (fixed to GPIO17, now UART RTS). GPIO12 serves as software/GPIO chip select only. Verify firmware supports GPIO CS mode for this signal.
2. JTAG swap (pins 16/18) — confirm TMS=GPIO23, TDI=GPIO24 matches debug toolchain configuration.
3. UART pull-ups — 4.7kΩ to 3V3 required on TxD (pin 8), RxD (pin 10), RTS (pin 11), CTS (pin 36).
4. Full connector net list — verify no net is left floating or duplicated after changes.

Reference documents

• reference_pinout.md (Please/ESH10000671_R0/DOCS/)
• ESH10000597_R0_pinout_issues.md (Please/ESH10000671_R0/DOCS/)
• E-017: original 12-error finding

Observation (corrected 2026-06-15)

R53 (NM) bridges SHDN_N to U11 (74HCS74) /CLR (pin 13).

Correction: SHDN_N is driven by the PI4IOE5V6416 I²C GPIO expander (U1-3) — NOT by an RPi GPIO. Netlist: SHDN_N = R53-1, U1-3, U3-1 (ECS-3225MV osc EN), J9-138 (SO-DIMM), R12-1. RPi GPIO13 / M1 pin 33 is I2CSEL4, a separate net. The earlier "RPi GPIO13 drives /CLR low early in boot" framing — also echoed in E-044 — is therefore incorrect.

Power-on behaviour

• U1 (PI4IOE5V6416) powers up with all I/Os as inputs (hi-Z) → U1-3 does not actively drive SHDN_N at POR.
• With R53 NM, U11 /CLR is held high by R54 (10k) → VCC ⇒ power latch holds, board powers on. This pull-up acts on /CLR only; it does not reach SHDN_N while R53 is unpopulated.

Decision (2026-06-15)

Leave R53 NM for R1. Latch held via R54→VCC; firmware soft-shutdown path intentionally disabled (consistent with the always-on direction, E-012/E-015). May experiment with populating R53 in a later build — doing so would both pull SHDN_N high (via R54) and enable the shutdown path.

Residual (RESOLVED 2026-06-15)

Pull-up added so SHDN_N defaults high (U3 oscillator enabled) at POR while U1 is hi-Z: R12 = 10kΩ from SHDN_N to 3V3 at the U3 (ECS-3225MV) EN input. Confirmed in schematic sheet 3, BOM (R12 now 10k, EGP10000097), and netlist (SHDN_N…R12-1, R12-2 = 3V3). NB: R12 was repurposed from a 0Ω strap at the TPS2373 MPS_DUTY pin (U12-9), which is now tied directly to GND — see follow-up question on that.

Follow-up

DL-012 (carried from R0 — RPi header loose fit, satisfied in R1 by [[REQ-026]] "no perceptible rattle when mated") should be resolved by a mechanical solution rather than by selecting a different/tighter connector component, if feasible.

Question to resolve

Can the RPi header rattle be eliminated mechanically — e.g. retention bracket/clip, board-to-board standoff or mechanical support, panel-side capture, or an interposer/spacer — instead of changing the connector part number?

Why prefer mechanical

• Avoids a connector reselection / footprint change this close to tape-out (MS-001, 2026-06-15).
• Keeps BOM and footprint stable; lower risk than a new component qualification.
• A mechanical fix may also address the related RPi connector alignment / protrusion requirement ([[REQ-027]], ex-DL-014) in one go.

Next step

• Mechanical to assess retention options against the Hammond enclosure stackup and front-panel interface before layout sign-off.
• If no mechanical solution is viable, fall back to connector reselection and capture the decision.
• Confirm chosen approach satisfies REQ-026 acceptance (no rattle when handled).

Update 2026-06-15

0.5 mm protrusion fixed — RPi connector repositioned in the layout (addresses the REQ-027 alignment/protrusion item). Still open: confirm whether the rattle / loose-fit (REQ-026) is also resolved by this move, or whether it still needs a mechanical retention solution.

Bus-to-connector routing intent (R1)

Captured allocation of the serial/debug buses across the module connectors — SO-DIMM (J9), M.2 (J15), N-Top (J10/J11/J12), Comtop (J3), RPi header (M1).

Notes / to verify against schematic

• SPI0 serves the RPi-side module stack (SO-DIMM + N-Top); SPI1 is dedicated to the M.2 ↔ Comtop path.
• UART and JTAG are distributed to all four module connectors (M.2, SO-DIMM, N-Top, Comtop).
• Cross-check against related requirements: [[REQ-037]] (SPI0 to SO-DIMM J9 — SCK/MOSI/MISO/CS0_N/CS1_N), [[REQ-038]] (UART to SO-DIMM J9), [[REQ-036]] (T1DATA[0:95] SO-DIMM↔N-Top bus), and the M1 connector pinout in [[E-019]] (SPI0 pins 19/21/23/24/26; SPI1 pins 12/32/35/38/40; UART pins 8/10/11/36; JTAG pins 15/16/18/22).
• ⚠️ Confirm consistency with E-019 pin 32 (GPIO12 = SPI1_CS1_N, software GPIO CS only) for the SPI1→Comtop chip-select.

RPI_ON (RPi 3V3 output, M1 pin 1) must be connected to a test point in the schematic.

RPI_ON indicates that the Raspberry Pi is powered and running. A test point on this net is required for bring-up and debug verification of RPi power state.

Required action

• Add test point component to RPI_ON net in schematic.
• Include test point in BOM and layout.

Update 2026-06-15

Test point added to RPI_ON in the schematic — netlist now shows RPI_ON = M1-1 + $3I7770-1 (previously a one-pin net), and a TP symbol appears on sheet 1. Remaining: the symbol is still unannotated (TP? — no reference designator) and is not yet in the BOM. Keeping open until the test point has a refdes and is reflected in BOM + layout.

TPS2373-4RGWR PG (Power Good) output is currently left floating in R1 schematic. PG is open-drain and would require a pull-up resistor and connection to a monitoring input.

Routing to ADS7828 was considered but rejected: using 2.5VREF as pull-up risks destabilising the ADC reference; a 3.3V divider adds unnecessary complexity for R1.

GPIOs are available on the RPi 4B interface. A 10kΩ pull-up to 3.3V with direct GPIO connection is viable in a future revision. PG would enable firmware-level PoE power sequencing and fault detection.

LM76005RNPR PG (Power Good) output is currently left floating in R1 schematic. PG is open-drain and indicates when the regulated output has reached its target voltage.

Routing to an RPi GPIO with 10kΩ pull-up to 3.3V would allow firmware to confirm the 20V bus is stable before enabling downstream loads. GPIOs are available on the RPi 4B interface.

Consider routing in R2 alongside TPS2373 PG for a complete PoE power chain status view.

The Group 5 schematic correction swapped JTAG TMS/TDI on M1 connector pins 16/18, but this swap was incorrect. The original assignment was already right:

• Pin 16 (GPIO23): TDI ← correct, must be reverted in schematic
• Pin 18 (GPIO24): TMS ← correct, must be reverted in schematic

User confirmed 2026-06-12. Schematic to be updated accordingly.

During Group 8 I2C annotation work, two items could not be resolved from available sources:

1. 0x0C — unknown device. LTC2992 (EGP10001605) uses 0x0C as its SMBus Alert Response Address — if LTC2992 is on this board, 0x0C is its ARA. Otherwise source is unknown.
2. 0x22 vs 0x23 (CH224Q, U27) — datasheet states "0x22 or 0x23" for CH224Q/CH224A. Current hypothesis: CH224Q = 0x22, CH224A = 0x23 (variant-fixed). Needs confirmation against actual device behaviour or WCH errata.

Action: Confirm both during schematic/netlist review before tape-out.

Observation

C50 (EGP10001913, A700X227M006ATE007) is rated 6.3V and placed on the 5V output rail (confirmed schematic page 12: "220u, 6.3V").

6.3V / 5.0V = 1.26× derating ratio. Standard practice for aluminium electrolytics is minimum 1.5× (ideally 2×) to account for:

• Voltage ripple on rail
• Component tolerance
• Temperature-dependent voltage derating

Risk

Early capacitor failure; reduced service lifetime.

Recommendation

Replace C50 with a 220µF/10V (or higher) electrolytic. EGP number will need to be updated. C49 (EGP10001791, A782MS227M1VLAS020) is rated 35V on VIN — that part is correctly derated.

Observation

Netlist unconnected pin list includes U17-7 and U17-23 without "(by TERM)" — meaning no explicit NC flag was placed in the schematic for these pins.

The LM76005RNPR schematic symbol includes NC1–NC7 labeled pins (13, 14, 15, 29, 27, 21, 20) which are correctly marked unconnected. Pins 7 and 23 are separate and their function needs verification.

Risk

If pins 7 and 23 are functional (e.g., AGND, PGND, or SYNC/MODE) the converter may malfunction. If they are truly NC by datasheet, missing NC markers are an ERC cleanliness issue.

Required action

Check LM76005RNPR datasheet for physical pins 7 and 23 (WQFN-30 package). If NC: add NC flags in schematic to suppress ERC warnings. If functional: connect appropriately.

Observation

SharpMES EGP10001392 (DS1813R-10+T&R) has assetType=Consigned, consignee=GBox. This part is not in E-Sharp inventory — it belongs to GBox and cannot be freely used on other products.

Risk

BOM submission for ESH10000597 R1 will require GBox approval or sourcing of a non-consigned alternative. DS1813R-10 is the Analog Devices supervisory reset IC.

Recommendation

Either obtain GBox agreement for this BOM usage, or find an equivalent non-consigned supervisory reset (e.g., MAX809, MCP101, similar SOT-23 3-pin reset IC) and create a new EGP.

The ESH10000597 R1 schematic (updated 2026-06-15) has been sent to colleagues for peer review. Two areas are flagged as extra important and should get focused attention:

1. M1 RPi connector pinout — see open notices [[E-018]] (8 pin reassignments vs R0) and [[E-017]] (12 functional pin-assignment errors found vs ESH10000539 reference). Verify GPIO-to-signal mapping, JTAG TMS/TDI (pins 16/18), SPI1_CS1_N on GPIO12 (pin 32, software CS only), and UART pull-ups before tape-out.

2. Secondary Power In (schematic sheet 10) — PoE chain: U12 (TPS2373-4 PD controller) + U17 (LM76005 buck) fed from VPOE / external 24–60 V (J16). Review classification resistors, input-cap voltage ratings (100 V parts), and the PG-pin handling ([[E-031]], [[E-032]]).

Reviewers: record findings as Trace entries against this project.

Decision (2026-06-15)

Connect both spare ADS7828 channels:

• CH_temp — board temperature via TMP236A4DCKR (EGP10001708; TI analog temp sensor, SC-70-5, 3V3 supply, ~19.5 mV/°C). Output reaches the 2.5 V VREF ceiling at ~82 °C — accepted for board-ambient over-temp telemetry (saturation = over-temp flag).
• CH_3V3 — 3V3 rail monitor via ÷2 divider + RC.

Kept after RPi-sensor check (2026-06-16)

RPi SoC has its own die-temp sensor but reads the Pi die only; TMP236 monitors the M1 carrier / power-stage thermal domain the Pi cannot see. Retained. Layout: place near the power-stage hot zone.

Implementation verified

• TMP236 = U14: U14-4=3V3 (decoupled by C35), U14-2=GND, U14-3=OUT → R78 → BOARD_TEMP (C32=100 nF to GND) → U24-3 (CH2). U14-1/-5 = NC.
• R78 = 1 kΩ (changed from 30 Ω) → RC cutoff ~1.6 kHz; resolves the TMP236 capacitive-load stability concern (1 k series before the 100 nF). Still ~1000× the temperature bandwidth.
• C35 added as U14 V+ decoupling (3V3↔GND).
• 3V3 monitor: 3V3 → R77 (1 k) → MON_3V3 → U24-4 (CH3) → R62 (1 k) → GND = ÷2 → 1.65 V.
• Both spare ADS7828 channels connected; no longer in the unconnected-pin list.

Status

Schematic + netlist + BOM verified (2026-06-16). Layout placement + clean DRC still pending — close E-043 once those are done.

Pre-layout schematic+BOM review (board 5, no ODB++ yet). Walked 7 active sheets (1 RPi & Bus, 2 Monitor/LED, 3 Fan/EEPROM/Clock, 9 USB-C Power In, 10 Secondary Power In, 11 Power Control, 12 Local Power); understanding 214/217 parts. Grounded in the Trace intent.

VERIFIED — implementation matches the recorded decisions:

• E-033 JTAG: R1 wires TDO=GPIO22(15), TDI=GPIO23(16), TMS=GPIO24(18), TCK=GPIO25(22) = the retained R0 order. CORRECT.
• E-016 5V->RPi: F1 2A in parallel with R147 0R (two-variant footprint). Present.
• E-028/29/30 TPS2373: CLSA=62R, CLSB=91R, AMPS_CTL=1k. Match.
• E-027 LM76005 CIN 10u/100V; E-035 L3+L4=20uH, feedback ~21V. Match (see reconcile below).
• E-031 TPS2373 PG + E-032 LM76005 PGOOD: both NC. CONFIRMED.
• E-007 U10 ILIM R39=680R; E-008 dVdt ramp C24/C22. Match.
• E-041 D3 SRV05-4 pin5 NC (correct for the -4LA). CONFIRMED.
• E-043 ADS7828 (U24) CH2/CH3 unconnected. CONFIRMED (2 spare ADC channels).

RECONCILE / RESOLVE:

• E-036 I2C address map RESOLVED on I2C0 (SDA0/SCL0): U1 PI4IOE=0x20, CH224Q=0x22 (resolves the 0x22-vs-0x23 question -> 0x22), LP5012=0x14, MAX6650=0x48, ADS7828=0x49, 24AA02 EEPROM=0x50-0x57. No address collisions. NO device on the schematic uses 0x0C -> the '0x0C unresolved' note appears stale or refers to an off-board/module device; suggest closing the on-board part of E-036.
• E-035: decision text says R_top=1x200k, but the schematic implements the LM76005 feedback top as 2x100k in series (R75+R56). Same value/ratio (~21V) - update the decision text to match.

OPEN / VERIFY:

• E-020 CONFIRMED: R53 (1k) in the SHDN_N(GPIO13)->U11 /CLR path is NM, and /CLR is pulled to VCC via R54 10k -> firmware soft-shutdown is non-functional as drawn and the latch power-up state is indeterminate. Decide intended boot state / whether R53 must be populated.
• 7805 (U13): raised as CON-001 (21V->5V drop on the always-on rail; VCC=5V vs E-015 '3V3' wording; E-013 footprint). See the concern.
• VIN architecture (confirm intended): VIN is a diode-OR of PoE (D14/D15) + external 24-60VDC (J16/D18) + USB-C 20V PD (J13/D16).

NOT YET WALKED (lower priority, mostly connectors): sheets 6/7/8 (module connectors J10-12/J3/J15 - relevant to E-018 RPi/module pinout & E-025 20V-VIN-on-module-pins), 13 (HDMI J6/J8), 4/5 (blank/notes). M2/M3/M5 (SMTSO standoffs) should be classified non-functional.

— odb board 5 (pre-layout walk)

Subject: Accordion M1 R1 — pre-layout schematic walk

— odb board 5 (comment)

Correction (2026-06-15, gustav.kihlberg)

The E-020 line above is superseded: SHDN_N is driven by the PI4IOE5V6416 (U1-3), not RPi GPIO13 (M1 pin 33 / GPIO13 is I2CSEL4). U1 powers up hi-Z, so the "GPIO13 drives /CLR low at boot" root cause does not apply. See corrected/closed E-020: R53 left NM for R1, latch held by R54→VCC, and a pull-up added at U3 (ECS-3225MV) EN to define SHDN_N high at POR.

U13 (7805) regulates the VIN bus (~21V) down to VCC (5V) — a ~16V linear drop on the always-on rail. Verify before layout: (1) worst-case dissipation — VCC must be a micro-load (the U11 74HCS74 latch only) for a 7805 at 21Vin to be thermally OK, and VIN can rise under PoE/PD transients; confirm what else loads VCC. (2) E-013's suspected 7805 footprint/part inconsistency must be resolved. (3) E-015 calls this the 'always-on 3V3 supply', but the part is a 7805 and OUT=VCC=5V — reconcile whether the always-on rail is 5V, or a downstream 3V3 LDO is intended/missing.

Receipts: ["schematic:sheet9 U13 7805 IN=VIN OUT=VCC (C25 100n)", "schematic:VIN ~21V diode-OR (D14/D15 PoE, D16 USB-C VBUS, D18 ext 24-60VDC; LM76005 E-035)", "trace:E-013 7805 footprint/part inconsistency — verify before layout sign-off", "trace:E-015 7805 retained as always-on supply for U11 74HCS74 latch (describes it as '3V3')", "bom:U13 = 7805 (EGP10001679)"]

— odb board 5, concern CON-001

Summary

DRC on the ESH10000597 R1 layout (PCB file agent_mini.pcb). Headline count is high but the overwhelming majority are configuration artefacts and expected-by-design items. DrcViolationsErrorLog.txt is empty (0 bytes) — no item-level export.

Resolved (earlier runs)

• Unplaced parts → 0; dangling vias/jumpers → 0; LM76005_OUT plane error → resolved; SMD-pad↔via clearance → No Hazards; vias-under-SMD-pads 7 → 2.

Reviewed and accepted by engineer (not defects)

• Trace hangers (25), trace loop (1), trace widths (4): inspected — not real violations. Recommend waiving/approving in the tool.

Open items before sign-off

• Vias under SMD pads: 2 — confirm intentional via-in-pad (filled/capped) or relocate.
• NEW (DRC re-run 2026-06-16 17:13) — 2 connectivity hazards from the added parts (both were "No Hazards" in the prior run):
  • Unrouted Pins: 1 — one pin not yet routed.
  • Plane Unrouted / Partially Routed Nets: 1 — a plane net (GND/3V3) not fully connected.
  • Almost certainly the newly added temp-sensor / 3V3-divider / battery circuitry (BOARD_TEMP, MON_3V3, VBAT B1+R80, C35 decoupling) — finish routing and re-run. Item-level location not in export; identify in the tool.

Informational / expected (no action)

• Vias under top/bottom place outlines: ground-stitching / via-in-pad under components.
• Component courtyard overlaps: M1 (RPi header) / J9 (SO-DIMM) over intentionally-placed parts; type-to-type clearance rules undefined (0.1 mm default).
• Board outline ↔ mounting holes: edge tab/mounting features, expected.

J15 (Accordion M2 slot) exposes a VBatt rail (pin 75, fed by a 'VBAT' rail label), but the M1 mainboard has no on-board battery or charger. Verify the source/intent of VBatt: (a) reserved/unconnected on R1, (b) fed from an external source, or (c) expected to be supplied BACK by the mating M2 module. If unconnected, any module relying on VBatt sees a dead rail; if module-sourced, confirm direction + protection. Decide and annotate before layout.

Receipts: ["schematic:sheet8 J15.75 VBatt + 'VBAT' rail label feeding it", "bom:M1 has no battery connector and no charger IC", "context:J15 is the main M2 expansion slot (75-pin)"]

— odb board 5, concern CON-002

SUMMARY of the pre-layout schematic+BOM review (board 5, no ODB++). 13 sheets walked, 214/217 parts understood, grounded in Trace intent. All findings are now discrete, tracked Trace entries (not just notes):

FINDINGS — live status:

• E-045 (CON-001) 7805 (U13) 21V->5V always-on rail — RAISED & ANSWERED (engineer): SOT-89 ~400mW, VCC is a light load (latch + pull-ups + LED, ~25mA) so dissipation is within rating; 5V is correct (3.3V would dissipate more); footprint resolved (E-013 closed); E-015 '3V3' wording corrected. CLOSED-OUT.
• E-047 (CON-002) VBatt on the M2 slot (J15.75) — OPEN: M1 has no on-board battery/charger; verify whether VBatt is reserved/unconnected, externally fed, or module-supplied, and annotate. Action before layout.
• E-020 R53 NM soft-shutdown — CONFIRMED from sheet 11 (R53 NM, /CLR held by R54 -> SHDN_N can't clear the latch). OPEN pending the firmware GPIO13 boot-state characterisation.
• E-025 12V->20V on module pins — on-board side CONFIRMED (VDD~=20V on J10/J3/J15 power pins, no 12V pin). OPEN: module-SIDE review (every mating N-Top/Comtop/M2 module must expect 20V, not 12V) — needs the module pinouts.
• E-036 I2C address map — CLOSED (clean map on I2C0; CH224Q=0x22; no on-board 0x0C).
• E-035 LM76005 R_top — CORRECTED (2x100k series, as built).

VERIFIED correct, no action: E-007 (ILIM 680R), E-008 (dVdt ramp), E-016 (5V fuse||R147), E-027 (CIN 10u/100V), E-028/29/30 (TPS2373 62R/91R/1k), E-031/032 (PG pins NC), E-033 (JTAG TDI=GPIO23/TMS=GPIO24), E-041 (D3 pin5 NC), E-043 (ADS7828 CH2/3 spare).

E-042 (the review ask) addressed: RPi pinout (sheet 1, M1 header — E-018/E-033) and Secondary/Main Power In (sheets 9/10) both walked. VIN = diode-OR of PoE + external 24-60VDC + USB-C 20V PD.

STILL NEEDS A HUMAN / MODULE DATA: E-047 (VBatt source), E-025 (module-side 20V), E-020 (firmware GPIO13), and the E-018 mechanical/full RPi-pinout sign-off.

NOTE on scope: this is a pre-layout review — connectivity-level checks (shorts, single-point nets, drive conflicts) are NOT run yet; they light up automatically when the post-layout ODB++ take ingests onto this same design line, and diff/fix-report will then show what layout implemented + cleared.

— odb board 5 (pre-layout review summary)

Subject: Accordion M1 R1 — pre-layout review SUMMARY (status of findings)

— odb board 5 (comment)

ERC-C01: I2CSEL3 (M1-31, GPIO6) and I2CSEL4 (M1-33, GPIO13) are single-pin nets — the signal names imply intended I2C-mux selection bits but the wires never reach the muxes (U4/U5). Should they be wired to a real consumer, or carry explicit no-connect symbols? Martin's disposition: should have no-connect symbol if not used.

Receipts: ["netlist:ESH10000597_NET.qcv lines 325-326 - I2CSEL3 M1-31 and I2CSEL4 M1-33 single-node entries", "netlist:I2CSEL0 has 3 nodes (U5-11, M1-28, U4-11) - pattern confirms 3 select bits per mux", "datasheet:SN74CB3Q3251PWR FUNCTION TABLE shows 3 select bits + OE only", "netlist:GND net includes U4-7 and U5-7 (OE pins) - muxes always-enabled"]

— odb board 5, concern CON-003

ERC-C08: RPi connector pins M1-1 and M1-17 are inconsistent with the recorded pinout table (E-019 / entry 410) which marks both as '3V3 Power'. RPi 40-pin spec confirms pins 1 and 17 are 3V3 OUTPUTS from the Pi (sourced from Pi's onboard LDO). Netlist shows M1-1 on RPI_ON net (with TP1-1) and M1-17 in unconnected list without (by TERM) marker. M1 has its own 3V3 generation via U8/U30 AMS1117 so it does not consume the Pi's 3V3 output. Martin's disposition: remove off-page symbol for pin 1, add no-connect symbol for pin 17, update pinout table (E-019).

Receipts: ["netlist:RPI_ON net = M1-1 TP1-1 (2 nodes)", "netlist:unconnected pins list contains '/M1 M1-17' without (by TERM)", "trace entry id 410 (E-019) - pin 1 and pin 17 rows say '3V3 Power'", "BOM:U8 = AMS1117-ADJ, U30 = AMS1117-ADJ (M1 generates own 3V3)", "RPi 40-pin spec: pin 1 = 3V3 output, pin 17 = 3V3 output (same rail)"]

— odb board 5, concern CON-004

ERC-C02: S2 (push-button PBH2UOANAHX) pins 4, 5, 6 are unconnected in the netlist AND lack the (by TERM) marker that every other intentional NC pin in the design carries. S2-1/2/3 are functional contacts. Pins 5/6 on 6-pin tactile switches are commonly mechanical retention tabs that may require ground per datasheet. Martin's disposition: add no-connect symbol.

Receipts: ["netlist:ESH10000597_NET.qcv lines 328-330 - S2-4, S2-5, S2-6 in unconnected list without (by TERM)", "netlist:lines 331-378 - all other unconnected pins have (by TERM)", "BOM:S2 = PBH2UOANAHX (push button, 6 pins)", "netlist:S2-1 on $14N73, S2-2 and S2-3 on $14N50 (only 3 of 6 pins functional)"]

— odb board 5, concern CON-005

ERC-D03: PG5 net (TPS259474 U16-3 Power Good output) is pulled up to 3V3 via R68 10k but has no consumer. The pull-up is wired, but no downstream logic, indicator, or sequencer reads the PG signal. Either route PG5 to its intended consumer (RPi GPIO for firmware power-state detection, indicator LED, etc.) or remove the off-page label and pull-up if no consumer is planned. Martin's disposition: PG5 goes nowhere, remove off-page if intentional.

Receipts: ["netlist:'PG5' U16-3 R68-1 (only 2 nodes)", "netlist:3V3 net contains R68-2 (confirms pull-up to 3V3)", "BOM:U16 = TPS259474LRPW (eFuse with PG)", "BOM:R68 = 10k (EGP10000097 group)", "trace entry E-031 (TPS2373 PG floating) and E-032 (LM76005 PG floating) - related PG-handling decisions"]

— odb board 5, concern CON-006

Schematic PDF (ESH10000597_SCH.pdf, 2026-06-15 export) has inconsistent sheet-count footers: sheets 1-8 read 'SHEET X of 12' while sheets 9-13 read 'SHEET X of 13'. Total sheets = 13 (the 'of 13' value is correct). Likely cause: sheet 9 (PoE secondary input) was added partway through R1 design and older sheets' page-count fields were not refreshed. Cosmetic but visible to anyone reviewing the released PDF. Martin's disposition: sheet numbering wrong.

Receipts: ["pdf:ESH10000597_SCH.pdf sheets 1-8 footer = 'SHEET X of 12'", "pdf:sheets 9-13 footer = 'SHEET X of 13'", "pdf:13 sheets present in total (extracted by pdftotext)", "Trace entry E-048 confirms '13 sheets walked' from pre-layout review"]

— odb board 5, concern CON-007

DESIGN REVIEW — Accordion M1 R1, post-layout take (ODB++ + BOM + schematic). Verdict: WARNINGS — 0 errors, 87 warnings. Classification/understanding coverage ~100% (513/514 members); distinct from the verdict and from electrical sign-off.

FINDINGS (3 rule clusters):

1. SinglePointNet x61 — nets reaching a single pin. Mostly unused connector / module-slot header pins (benign), but a subset may land on IC inputs (floating-input risk) — needs triage.
2. I2cPullupMissing x16 — all 8 I2C channels (SCL0-7 / SDA0-7) flagged as lacking a 2-pin pull-up to a rail.
3. BomLayoutMismatch x10 — placed but absent from BOM: J9 + NRD0-8 (9 no-load/DNP resistor positions).

INTENT: E-031 (TPS2373 PG) and E-032 (LM76005 PG) unrouted — confirmed; intended "GPIO for future". BOM linkage otherwise clean (225/225, 6 DNP incl. CR-1632 coin cell).

— odb board 7 (comment)

Dispositions 2026-06-16 (engineer + AI verify)

• I2cPullupMissing ×16 → FALSE POSITIVE. All 16 I2C lines have 10 kΩ pull-ups to 3V3 via resistor arrays: SDA0-3→R3, SDA4-7→R4, SCL0-3→R5, SCL4-7→R6 (EXB-N8V103JX, BOM line 36; R7/R8 = SRQ). Feed side on 3V3, signal side on SDA/SCL — verified in netlist. Review rule looked for discrete 2-pin pull-ups and missed the array packages. Pull-ups are ON-BOARD. Waived.
• BomLayoutMismatch J9 → REAL, being fixed. Root cause: J9 (SO-DIMM) had "Part List Exclude: True", silently dropping a real connector from the BOM export. Netlist↔BOM reconciliation confirmed J9 + TP1 as the only connected refdes missing (227 vs 225); TP1 is a benign bare-pad test point. Action: add J9 to the BOM. ← only open action from this review.
• NRD0-8 → could not be identified in netlist/schematic/BOM/layout; no function located. Disregarded.
• SinglePointNet ×61 → TRIAGED, no defects. Netlist = 52 single-connection pins (+ 9 NRD0-8 layout-only = 61). 29 are unused connector/switch/diode spares (J13/J15/J10/J6, M1-17/31/33, S2-4/5/6, D3-5 — already dispositioned E-041/049/050/051). 23 are IC pins, and EVERY one carries an explicit NC flag (by TERM) — no unmarked floating IC inputs. Of those: datasheet-NC (U14, U17, U19), open-drain PG outputs left open (U10-3, U12-13, U27-10), unused outputs/GPIO (U11-5/6/9, U21-6/7, U4-6/U5-6). Engineer-confirmed 2026-06-16: U12-16/17/18/19 (TPS2373 UVLO_SEL/TPL/TPH/BT — converter-control pins, unused since LM76005 does the buck) = NC by design; U2-5 (TPS54302 EN) = floats-to-enabled, always-on intended. No tie-offs required.

Found during R1 manual PCB review (2026-06-17): an earlier consultant routed copper for the 1V8 and 2V5 rails on/through a layer serving as a GND reference plane, breaking that plane's continuity.

Risk: a slotted reference plane under high-speed signals disrupts the return path — impedance discontinuity, crosstalk/EMI, degraded SI for any high-speed net crossing the affected region.

R1 disposition: NOT fixed in R1 (no time in the order timeline); assessed probably low impact; proceeded as-is.

Next-revision follow-up: reroute 1V8/2V5 off the reference layer (or re-pour a continuous GND plane); audit which high-speed nets cross the affected region; capture affected-net list + stackup detail.

Re-created after the 2026-06-17 Trace crash (was E-058).

JLCPCB's matcher auto-picked TE parts for the two custom E-Sharp connectors — these were machine "Select by System" matches, NOT engineer-confirmed:

• J9 (AccordionMPIO) → TE 2309413-1 (C2766246)
• J15 (Accordion M2 slot) → TE 2199230-5 (C4827729)

Action: confirm each is the correct mating connector (pinout, pitch, mechanical fit) for the custom part — or override / consign. Do not assume the auto-match is right.

Captured during R1 BOM review, 2026-06-17.