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Sparrow Active Load M.2 module

ESH10000536 · Rev R2

in_progresselectronics

Lightweight shell — full new_project workflow pending. Imported as dependency of ESH10000633 R1.

Reports Audit Log

Everything here lives inside a Project (a code + revision, e.g. ESH10000540 R3). The backbone is the V-model, read top-to-bottom: define what the product must do, plan how to prove it, execute the proof on real units, then learn from the field — and the Loop closes back up to the top.
This map is live: a block is green with a count when this project actually has that entity, and dashed/dim when it’s empty. Click any block to open its tab; hover for details. Arrows are the meaningful links; the implicit “belongs to this Project” edge is left out for legibility.

What each thing means

Requirement
One thing the product must do or satisfy — the “what”.
Test Case
A defined check that proves one or more requirements — the “how we prove it”. A verified_by trace link ties a test case to the requirement(s) it covers; that link is exactly what Coverage % counts. (So: a test case refers to the requirements it verifies.)
Verification Plan
A named grouping of test cases, approved before a test campaign and optionally gated by a milestone.
Verification Record
The result of running one test case against one unit: pass / fail / error / na. This is the evidence a requirement is actually met.
DUT
Device Under Test — an individual physical unit (by serial number) that records and test data attach to.
Deviation
A documented waiver against a verification record (e.g. accept a known non-conformance, with justification).
Entry
A knowledge note: a decision (settled choice), notice (assumption / risk / open question), issue (tracked problem), or concept (idea under exploration). It can attach to any other entity.
Design Rule
A reusable, checkable engineering constraint. Running the checks turns each violation into a Conflict.
Conflict
An open flag raised by a failed design-rule check (or an end-of-life / component-library issue) that needs resolving.
Milestone
A dated gate; verification plans can be tied to it.
Field Issue (RMA)
A failure reported from the field on a returned unit; Root-Cause Analysis explains why it happened.
The Loop (S-16)
loop_trace reconciles a field issue against that unit’s own verification record (did it pass at the edge of the band?). closes_loop records the corrective decision or design rule so the lesson is captured — and clears the project’s open-loop count.
Interface / Port
A contract between projects; each port can be driven by a requirement (and cascade one into the connected project).
BOM Component
A part on this project’s bill of materials, optionally linked to the shared Component Library.
GRR Study
A Gauge R&R study measuring how repeatable a test case’s measurement is.
Test Data
Production / Maestro run results recorded against DUTs — the population behind a single verification record.
0% Coverage
0% Done
0 Requirements
7 Test Cases
12 Open Entries

Timeline

Color = derived gate state · hover a tile for its note.
not started
🏁 Release
· 3/6

Status & gates

Chronological — Release is the final gate. Derived & read-only; edit via trace_milestone_* tools.
Release / Readiness not started 3/6 met
pending Requirements approved
  • REQ-EL-002: draft
  • REQ-EL-004: draft
  • REQ-EL-006: draft
  • REQ-EL-001: draft
  • REQ-EL-003: draft
  • REQ-EL-005: draft
  • REQ-EL-007: draft
pending Coverage ≥ 100%
  • No requirements in scope
pending All test cases pass
  • 0/7 passed
  • 7 not yet run
met No blocking issues open
met Deviations resolved
met Interfaces frozen
Attention 9 open entries

Test Cases

0 Pass 0 Fail / Deviated 0 N/A 7 Open0 / 7 Maestro impl.

Coverage — 0.0% · Done — 0.0%

0 Done 0 Partial 0 Not Started 0 Missing7 Draft0 Obsolete
Entries
12 of 12
CodeKindTitleSeverityScopeStatusMilestoneCreated
E-001 notice VLOAD*_OUT per-channel power analysis — loop-gain ceiling + thermal budget info record open — 2026-06-09
E-002 notice R3: investigate improved thermal coupling from Q1/Q2 to heatsink info next_revision open — 2026-06-09
E-003 notice R3: investigate why isolator U5 (ISOW7741) does not work — current workaround unmounts U5/Q4/R2/R3 and mounts R65–R69 warning next_revision open — 2026-06-09
E-004 notice DUT S/N A002854 — broken measurement on CH1 (J4) warning action open — 2026-06-09
E-005 concept FET+shunt damage may occur at load TURN-OFF (PSU overshoot + OPA2192 ringing → secondary-breakdown transient) info action open — 2026-06-09
E-006 concept R3 spec: hardware abuse-tolerance against load disconnects (TVS D-S clamp + V_LOAD-ceiling decision) info next_revision open — 2026-06-09
E-007 notice Rework: DUTs S/N A002872 + A002877 — replace shunt resistors + MOSFETs warning action open — 2026-06-09
E-008 notice Rework: DUT S/N A002874 CH0 (J4) — replace shunt + MOSFET warning action open — 2026-06-09
E-009 notice [E-003] Root-cause analysis of "I2C doesn't work through U5 (ISOW7741)" [E-003]. TOPOLOGY (read from schematic sheet 1): bidirectional SDA… info record open — 2026-06-18
E-010 concept Isolated-I2C replacement options for the U5/ISOW7741 bridge (E-003 fix, next revision) info next_revision open — 2026-06-18
E-011 issue AL board S/N A002878 — CH0 MOSFET shorted (second board with same fault mode after A002854) warning action open — 2026-06-18
E-012 issue AL board A002870 CH1: AL.02 marginal fail — IMEAS / PSU truth low by ~10 mA at 400 mA / 16 V (CH0 clean) warning action open — 2026-06-18