Micro-HAPS
ETT00000008 · Rev R0
in_progresstestelectronics
Micro-HAPS is a Synopsys-developed test board for at-speed (high-speed I/O) testing, based on a Xilinx Kintex UltraScale+ KU5P FPGA. This project covers E-Sharp's test development work on/with the board.
- Primary domain: test (at-speed test development)
- Secondary domain: electronics (KU5P FPGA-based board)
- Vendor: Synopsys (SNPS); HW designer Martin Wang
- PCBA: SH100008193-R0.0 (PCB SH100008192-R0.0 "KU5P_Generic_Tester"); 49×67 mm, 18-layer, impedance-controlled @1 GHz. Main device: XCKU5P-1 FFVB676; host control via FTDI FT4232H.
- ⚠ Design docs (schematic/BOM/spec) are SYNOPSYS CONFIDENTIAL; the customer BOM is not imported into the Trace component library (see decisions).
- Repository: https://github.com/esharpab/testdevelopment-snps-microhaps
Everything here lives inside a Project (a code + revision, e.g. ESH10000540 R3).
The backbone is the V-model, read top-to-bottom: define what the product must do, plan how to prove it,
execute the proof on real units, then learn from the field — and the Loop closes back up to the top.
This map is live: a block is green with a count when this project actually has that entity,
and dashed/dim when it’s empty. Click any block to open its tab; hover for details.
Arrows are the meaningful links; the implicit “belongs to this Project” edge is left out for legibility.
What each thing means
- Requirement
- One thing the product must do or satisfy — the “what”.
- Test Case
- A defined check that proves one or more requirements — the “how we prove it”. A verified_by trace link ties a test case to the requirement(s) it covers; that link is exactly what Coverage % counts. (So: a test case refers to the requirements it verifies.)
- Verification Plan
- A named grouping of test cases, approved before a test campaign and optionally gated by a milestone.
- Verification Record
- The result of running one test case against one unit: pass / fail / error / na. This is the evidence a requirement is actually met.
- DUT
- Device Under Test — an individual physical unit (by serial number) that records and test data attach to.
- Deviation
- A documented waiver against a verification record (e.g. accept a known non-conformance, with justification).
- Entry
- A knowledge note: a decision (settled choice), notice (assumption / risk / open question), issue (tracked problem), or concept (idea under exploration). It can attach to any other entity.
- Design Rule
- A reusable, checkable engineering constraint. Running the checks turns each violation into a Conflict.
- Conflict
- An open flag raised by a failed design-rule check (or an end-of-life / component-library issue) that needs resolving.
- Milestone
- A dated gate; verification plans can be tied to it.
- Field Issue (RMA)
- A failure reported from the field on a returned unit; Root-Cause Analysis explains why it happened.
- The Loop (S-16)
loop_tracereconciles a field issue against that unit’s own verification record (did it pass at the edge of the band?).closes_looprecords the corrective decision or design rule so the lesson is captured — and clears the project’s open-loop count.- Interface / Port
- A contract between projects; each port can be driven by a requirement (and cascade one into the connected project).
- BOM Component
- A part on this project’s bill of materials, optionally linked to the shared Component Library.
- GRR Study
- A Gauge R&R study measuring how repeatable a test case’s measurement is.
- Test Data
- Production / Maestro run results recorded against DUTs — the population behind a single verification record.
0%
Coverage
0%
Done
0
Requirements
6
Test Cases
1
Blockers
49
Open Entries
Timeline
Color = derived gate state · hover a tile for its note.not started
🏁 Release
Status & gates
Chronological — Release is the final gate. Derived & read-only; edit viatrace_milestone_* tools.Release / Readiness not started 2/6 met
pending Requirements approved
- REQ-TS-001: draft
- REQ-TS-002: draft
- REQ-TS-003: draft
- REQ-TS-004: draft
- REQ-TS-005: draft
- REQ-TS-006: draft
pending Coverage ≥ 100%
- No requirements in scope
pending All test cases pass
- 0/6 passed
- 6 not yet run
pending No blocking issues open
- E-045: open blocker
met
Deviations resolved
met
Interfaces frozen
Test Cases
0 Pass
0 Fail / Deviated
0 N/A
6 Open0 / 6 Maestro impl.
Coverage — 0.0% · Done — 0.0%
| Code | Title | Category | Coverage | Status |
|---|---|---|---|---|
REQ-TS-001 |
Requirement Coverage | coverage | — | — |
REQ-TS-002 |
Measurement Uncertainty | metrology | — | — |
REQ-TS-003 |
Calibration Interval | metrology | — | — |
REQ-TS-004 |
Pass/Fail Criteria | quality | — | — |
REQ-TS-005 |
Repeatability (GR&R) | metrology | — | — |
REQ-TS-006 |
Test Limit Derivation Documented | quality | — | — |