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Micro-HAPS

ETT00000008 · Rev R0

in_progresstestelectronics

Micro-HAPS is a Synopsys-developed test board for at-speed (high-speed I/O) testing, based on a Xilinx Kintex UltraScale+ KU5P FPGA. This project covers E-Sharp's test development work on/with the board.

  • Primary domain: test (at-speed test development)
  • Secondary domain: electronics (KU5P FPGA-based board)
  • Vendor: Synopsys (SNPS); HW designer Martin Wang
  • PCBA: SH100008193-R0.0 (PCB SH100008192-R0.0 "KU5P_Generic_Tester"); 49×67 mm, 18-layer, impedance-controlled @1 GHz. Main device: XCKU5P-1 FFVB676; host control via FTDI FT4232H.
  • ⚠ Design docs (schematic/BOM/spec) are SYNOPSYS CONFIDENTIAL; the customer BOM is not imported into the Trace component library (see decisions).
  • Repository: https://github.com/esharpab/testdevelopment-snps-microhaps
Reports Audit Log

Everything here lives inside a Project (a code + revision, e.g. ESH10000540 R3). The backbone is the V-model, read top-to-bottom: define what the product must do, plan how to prove it, execute the proof on real units, then learn from the field — and the Loop closes back up to the top.
This map is live: a block is green with a count when this project actually has that entity, and dashed/dim when it’s empty. Click any block to open its tab; hover for details. Arrows are the meaningful links; the implicit “belongs to this Project” edge is left out for legibility.

What each thing means

Requirement
One thing the product must do or satisfy — the “what”.
Test Case
A defined check that proves one or more requirements — the “how we prove it”. A verified_by trace link ties a test case to the requirement(s) it covers; that link is exactly what Coverage % counts. (So: a test case refers to the requirements it verifies.)
Verification Plan
A named grouping of test cases, approved before a test campaign and optionally gated by a milestone.
Verification Record
The result of running one test case against one unit: pass / fail / error / na. This is the evidence a requirement is actually met.
DUT
Device Under Test — an individual physical unit (by serial number) that records and test data attach to.
Deviation
A documented waiver against a verification record (e.g. accept a known non-conformance, with justification).
Entry
A knowledge note: a decision (settled choice), notice (assumption / risk / open question), issue (tracked problem), or concept (idea under exploration). It can attach to any other entity.
Design Rule
A reusable, checkable engineering constraint. Running the checks turns each violation into a Conflict.
Conflict
An open flag raised by a failed design-rule check (or an end-of-life / component-library issue) that needs resolving.
Milestone
A dated gate; verification plans can be tied to it.
Field Issue (RMA)
A failure reported from the field on a returned unit; Root-Cause Analysis explains why it happened.
The Loop (S-16)
loop_trace reconciles a field issue against that unit’s own verification record (did it pass at the edge of the band?). closes_loop records the corrective decision or design rule so the lesson is captured — and clears the project’s open-loop count.
Interface / Port
A contract between projects; each port can be driven by a requirement (and cascade one into the connected project).
BOM Component
A part on this project’s bill of materials, optionally linked to the shared Component Library.
GRR Study
A Gauge R&R study measuring how repeatable a test case’s measurement is.
Test Data
Production / Maestro run results recorded against DUTs — the population behind a single verification record.
0% Coverage
0% Done
0 Requirements
6 Test Cases
1 Blockers
49 Open Entries

Timeline

Color = derived gate state · hover a tile for its note.
not started
🏁 Release
· 2/6

Status & gates

Chronological — Release is the final gate. Derived & read-only; edit via trace_milestone_* tools.
Release / Readiness not started 2/6 met
pending Requirements approved
  • REQ-TS-001: draft
  • REQ-TS-002: draft
  • REQ-TS-003: draft
  • REQ-TS-004: draft
  • REQ-TS-005: draft
  • REQ-TS-006: draft
pending Coverage ≥ 100%
  • No requirements in scope
pending All test cases pass
  • 0/6 passed
  • 6 not yet run
pending No blocking issues open
  • E-045: open blocker
met Deviations resolved
met Interfaces frozen
Blocked 1 blocking entry

Test Cases

0 Pass 0 Fail / Deviated 0 N/A 6 Open0 / 6 Maestro impl.

Coverage — 0.0% · Done — 0.0%

0 Done 0 Partial 0 Not Started 0 Missing6 Draft0 Obsolete
Entries
56 of 56
CodeKindTitleSeverityScopeStatusMilestoneCreated
E-001 notice Micro-HAPS board context: Synopsys at-speed test board, Xilinx KU5P FPGA info record open — 2026-06-04
E-002 decision Engagement scope: E# to deliver turn-key microHAPS production test fixtures; SNPS buys turnkey info record open — 2026-06-04
E-003 decision Control interface: HCI (Host Controller Interface) over full UART via FTDI info record open — 2026-06-04
E-004 decision Mechanics: keep open-frame ATX enclosure; custom top plate per DUT info record open — 2026-06-04
E-005 decision Hardware rollout: Rev0 microHAPS to E# to start; target Rev1 for formal deployments info record open — 2026-06-04
E-006 notice microHAPS board architecture & control (per Dave Upton) info record open — 2026-06-04
E-007 notice microHAPS cleanup/final revision in progress — RC schematic to be shared for E# review warning action open — 2026-06-04
E-008 notice Open questions: firmware/RTL ownership, FTDI-vs-header control, host PC vs Raspberry Pi warning action open — 2026-06-04
E-009 notice ACTION: define formal engagement mechanism; SNPS to provide DUT timeline needs warning action open — 2026-06-04
E-010 notice microHAPS PCBA fabrication spec (PCB SH100008192 / PCBA SH100008193) info record open — 2026-06-04
E-011 notice microHAPS PCBA functional architecture (from schematic/BOM) info record open — 2026-06-04
E-012 decision microHAPS BOM intentionally NOT imported into PLEASE component library (customer IP) info record open — 2026-06-04
E-013 notice MicroHAPS R0.0 HW verification — HCI FPGA designs & at-speed SSTDM results (Erik Ingemarsson) info record open — 2026-06-04
E-014 notice MicroHAPS adapter cards (3) & NVAM loopback cables info record open — 2026-06-04
E-015 notice MicroHAPS R0.0 bring-up / power-up procedure info record open — 2026-06-04
E-016 notice INCOMING MicroHAPS R1.0: big black switch removed, Service Port in AWO domain, automated 12V warning next_revision open — 2026-06-04
E-017 notice MicroHAPS host setup & toolchain (NI MAX Service Port, Python/Tcl/Vivado Lab) info record open — 2026-06-04
E-018 notice MicroHAPS resource locations — SharePoint, Empower, Perforce verification stream info record open — 2026-06-04
E-019 notice OpenOCD / XVC server config for FT4232H JTAG (xvc_server.cfg) info record open — 2026-06-05
E-020 concept TODO: Build a native Accordion extension for MicroHAPS (drop the Synopsys vivado/hci/synplex dependency) info action open — 2026-06-05
E-021 notice MicroHapsHandler extension scaffolded in accordionq2 info action open — 2026-06-05
E-022 notice MicroHapsHandler: transport migrated + MPSSE I2C implemented — builds green info action open — 2026-06-05
E-023 notice FTD2XX native loader made cross-platform (linux-arm64 blocker resolved) info record open — 2026-06-05
E-024 notice MicroHapsHandler: native libftd2xx scaffolded (RID-driven); host arch still open info action open — 2026-06-05
E-025 decision MicroHAPS Accordion host = Raspberry Pi (linux-arm64) info record open — 2026-06-05
E-026 notice FT4232H: A/B/C/D are independent interfaces; only A/B have MPSSE info record open — 2026-06-05
E-027 notice MicroHapsHandler: HCI port (FTDI C) wired via Synopsys.HciBus — builds green info action open — 2026-06-05
E-028 notice MicroHAPS R0 Service Port (FT4232H) identity & interface map (from Pi by-id) info record open — 2026-06-05
E-029 notice Bring-up console (microhaps-bringup) built — first hardware smoke test (no ftdi_sio setup) info action withdrawn — 2026-06-05
E-030 notice Non-root USB/D2XX access confirmed on agent64 — no sudo / udev rule needed info record open — 2026-06-05
E-031 notice MicroHapsHandler: Port A (XVC/JTAG) + Port D (GPIO) implemented — all 4 drivers done, builds green info action open — 2026-06-05
E-032 notice MicroHaps implemented as an Accordion Module (channels + IBusHandler I2C); registered + builds info action open — 2026-06-05
E-033 notice HCI: cloned the HciHandler module into the extension, retargeted UART to FTDI Port C info action open — 2026-06-05
E-034 notice MicroHAPS host bring-up working: I2C + power + JTAG IDCODE read on agent64 info record open — 2026-06-05
E-035 issue openFPGALoader doesn't drive the JTAG buffer enable (ADBUS5) — fixed in R1 (BDBUS4); R0 uses slow XVC info next_revision open — 2026-06-05
E-036 notice Install/boot requirement: detach ftdi_sio from the FT4232H so D2XX/openFPGALoader can claim the interfaces warning action closed — 2026-06-05
E-037 notice Host bring-up status: ftdi_sio detach + openFPGALoader path done; HCI link verification is next info action open — 2026-06-06
E-038 concept JTAG signal chain (FT4232 service port → KU5P) — open-drain TDO buffer (U9, 1.8V VCC + 10K pull-up to 3.3V) is the speed limiter; shared by FTDI & XJTAG warning next_revision open — 2026-06-06
E-039 notice ACTION: Physically verify C10–C13 mount status on real R0 board (PDF says NM, ODB++ says populated 10nF) warning action open — 2026-06-06
E-040 concept HCI Bus Specification (HCIBus) — reference for the microHAPS control protocol (UART/byte-wide; commands, device classes, registers) info record open — 2026-06-06
E-041 notice HCI bring-up SOLVED on R0.0 — interface D, 8-O-1, RTS/CTS; full chain enumerates info record open — 2026-06-06
E-042 notice I2C subsystem schematic walkthrough — R0 (pull-ups, domains, SCL/SDA, addresses) info record open — 2026-06-07
E-043 notice R0 I2C: FPGA↔mgmt-bus bridge is repeater U5, jumper-gated by J3 — NM in R0 build warning next_revision open — 2026-06-07
E-044 notice R0 I2C: management bus runs unbuffered on a single FTDI-segment 1k pull-up to P3V3_G warning record open — 2026-06-07
E-045 issue R0 I2C: Si5340 (CLKA) FET level-translator Q22/Q23 wired backwards — main 3V3 bus clamped via Si5340 1.8V ESD blocking next_revision open — 2026-06-07
E-046 concept I2C Bus B (MUX_I2C) — PCA9547 U47 fan-out diagram info record open — 2026-06-07
E-047 notice R0 I2C buffer/translator pull-up audit — both sides & rail voltage info record open — 2026-06-07
E-048 issue R0 BLOCKING: FTDI service port cannot control the LTC2980 power manager — bus V_OL (0.4V) exceeds LTC2980 V_IL blocking action closed — 2026-06-07
E-049 issue R0 BOM↔schematic mismatch: U56 buffer & R558/R559 bypass populate/DNI are SWAPPED (board built unbuffered, contrary to schematic) warning action open — 2026-06-07
E-050 notice ACTION (Daniel, ~2026-06-08): fit U56 TCA9803 on R0 + REMOVE R558/R559 + fix EN strap (R557), test LTC2980 warning action closed — 2026-06-07
E-051 issue Host SW: module unload leaked openFPGALoader --xvc process + FT4232H handles — every MicroHAPS reload failed (fixed) warning record closed — 2026-06-08
E-052 issue BLOCKING: LTC2980 (0x5C/0x64) ACK address but NACK every command (incl. STATUS_BYTE) after U56 rework — buffered-segment integrity issue, not config blocking action closed — 2026-06-11
E-053 notice DESIGN FLAW: two TCA9803 static-offset buffers (U56 + U5) drive the same I2C segment with no enable orchestration — buffers latch / V_OL stacks; bites in R1 (U60+U5 both fitted) warning next_revision open — 2026-06-11
E-054 notice ODB++ shows U5 (TCA9803) POPULATED with its B-side ports (pins 6/7 = SDAB/SCLB) on I2C_SDA0 / I2C_SCL0 alongside U56 — two static-offset I2… info record open — 2026-06-14
E-055 notice [net:JTAG_TDO_3V3] Probe's connectivity review independently corroborates E-038 (open-drain TDO buffer = JTAG-speed limiter). On JTAG_TDO_3… info record open — 2026-06-14
E-056 notice [component:U1] Micro-HAPS R0 — Probe review triage of the WARNING-severity findings (the 2 errors are disposed separately: CON-001 = I2C bu… info record open — 2026-06-14