Hypothesis

For Phase B, E# will propose a platform with interchangeable top panels to support multiple DUTs.

Scope sketch

• Includes Micro HAPS PCBa + adapter cards, but not the Micro HAPS chassis.
• The interchangeable top panels may be reused if they can be adapted into a new platform design.

Open questions

• How much further development is needed to complete the platform? Any such work is to be handled in a separate SOW, preferably completed before September 2026.

Next step

• E# to prepare the Phase B platform proposal (action item).

Hypothesis

Briefly discussed (2026-06-03): a potential Phase C in which E# may propose an alternative solution for high-speed testing, as an alternative to using the Micro HAPS PCBa.

Note

This is likely where at-speed / high-speed coverage lands for the program — cf. the at-speed scope gap flagged in E-010 (at-speed was excluded from Phase A / E#'s quote).

Next step

Initial discussion only; no commitment yet. Revisit after Phase A/B.

B12-N_PB — Production Test Specification

DUT: B12-N Panel Board (B12-N_PB), SH100008620 Test platform: microHAPS (KU5p test board, SH100008193) + HT3x2-HT4x2 adapter (SH100008643) + Snowball Trace project: ETT00000009 R0 · Probe board: id 28 (b12-n_pb_odb_sim_edm_0_62) Status: DRAFT v0.1 · derived from Production Test SOW for B12-N_PB + Probe connectivity/device review Author: daniel@esharp.se

⚠️ Open values: numeric limits, the VCCO negotiated range, MPM54304 PMBus register set, IDPROM content, and clock frequencies are marked [TBD] and must be confirmed against the B12-N_PB Implementation Specification, the IDPROM Content Spec V2 (SH100008620_R0.0_B12-N_PB_IDPROM_Content_Spec_V2.xlsx), and the Design Log before release (SOW §7 test-readiness review).

1. Purpose & Scope

Define a complete, automated, hands-off production test for every manufactured B12-N_PB unit, validating power, I/O connectivity, I²C accessibility, HT3/HT4 behaviour, voltage negotiation, telemetry, and board identity prior to integration/shipment, per the SOW.

In scope: the 8 functional test groups in §6 across all 5 channels, IDPROM programming, golden-unit verification, TestStand + Synplex integration, and the SOW deliverables (§11). Out of scope (SOW §2.2): system/board validation & characterization, repair procedures, firmware feature development beyond test enablement.

2. Device Under Test

HT3-to-HT4 panel board providing 5 independent channels (CON1–CON5). Each channel adapts a user-facing HT3 connector to an internal HT4 connector, with local power regulation, I²C, clock buffering, and VCCO voltage negotiation. Board is fed from a single 12 V input.

2.1 Per-channel functional blocks (from Probe review)

2.2 CON1-only

2.3 Power rails (per channel unless noted)

3. Test Architecture & Topology

flowchart TB
    HOST["Host PC<br/>TestStand + Synplex<br/>(sequencing / logging)"]

    subgraph ACC["Accordion Plus (Linux)"]
        direction TB
        ACCCTL["Test executive / instrument host"]
        PSU["12 V PSU<br/>(internal instrument, current-monitored)"]
        ACCCTL --- PSU
    end

    UHAPS["microHAPS (KU5p FPGA)<br/>TEST MASTER<br/>HCI HDL"]
    ADAPTER["HT3x2-HT4x2 adapter<br/>SH100008643"]

    subgraph DUT["B12-N_PB (DUT) — 5 channels"]
        direction TB
        HT4["JX1..JX5 (HT4, internal)"]
        PANEL["Per-channel routing<br/>power · I²C · CLK · VCCO · reset"]
        HT3["J1..J5 (HT3, user-facing)"]
        HT4 --- PANEL --- HT3
    end

    SNOW["Snowball x N (on HT3)<br/>endpoint / loopback / pattern sink"]

    HOST -->|control| ACCCTL
    ACCCTL -->|control| UHAPS
    PSU -->|"12 V — Source A → ME1 terminal"| DUT
    PSU -->|"12 V — Source B (HT4-side, O-10)"| ADAPTER
    UHAPS <-->|"PRIMARY control interface<br/>(SOW §2.1: HT4-side access)"| ADAPTER
    ADAPTER <-->|"HT4 signals + 12 V (Source B)"| HT4
    HT3 <-->|"loopback / capture"| SNOW

Two 12 V feeds (see Appendix E): Source A powers the DUT's ME1 terminal directly (runs the MPM54304/U18 regulators → V3P3/VCCO); Source B enters via the HT4 connector (V12P0_SRC_CONx, runs the per-channel TPS71501 → V1P8 / I²C and the eFuse). Both originate at the Accordion PSU here; which side physically drives the HT4-side 12 V in the rig is O-10.

• Accordion Plus (Linux): sits between the host and microHAPS as the test executive / instrument host. Hosts the 12 V PSU as an internal instrument (programmable, current-monitored) that supplies the DUT on two feeds — Source A direct to the ME1 terminal, and Source B via the HT4 connector (V12P0_SRC_CONx) — and relays control/sequencing from the host PC to the microHAPS.
• microHAPS (HT4 side, via adapter): the test master. Its KU5p FPGA drives/captures the HT4 IO, sources at-speed patterns, drives I²C (through to the panel's I²C bus), asserts channel enables/reset, and reads back telemetry.
• Snowball (HT3 side): plugged onto each HT3 connector (J1–J5) as the user-side endpoint. Provides loopback / pattern capture so each HT4→panel→HT3 path is exercised end-to-end and at speed, and so VCCO/reset behaviour can be observed at the HT3 connector. (Snowball count: 1 per channel for full parallel coverage, or 1 indexed across channels for sequential coverage — see §9.)
• HDL: baseline HCI (GPIO-expander + I²C-master endpoints) for connectivity/I²C/power; an at-speed-capable HDL image for HT3/HT4 fast-speed testing [at-speed HDL TBD — see O-8].

4. Test Equipment & Fixtures (Fixture BOM)

5. Test Access Map

• Control interface: HT4 (JX1–JX5) via adapter → microHAPS. All programming and stimulus enter here (SOW §2.1).
• I²C topology per channel: microHAPS I²C → HT4 → main bus CONx_SCL_IN/SDA_IN (1.81 V, pull-ups to V1P8) → A-side of the channel's TCA9803 buffers (2× on CON2–CON5, 3× on CON1) → level-translated, isolated B-side segments: _IN_V3P3 (AD5593R 0x10 + MPM 0x68), _IN_HT3 (to HT3/DUT), and on CON1 _EEPROM (M24C02 0x50). See Appendix D.
• Power topology: two 12 V inputs — ME1 (Accordion PSU) → V12P0 → MPM54304/U18 regulators; and HT4 (V12P0_SRC_CONx) → per-channel TPS71501 (V1P8) + eFuse. DUT receives only regulated V3P3_CONx/VCCO_CONx at HT3. See Appendix E.
• Per-channel I²C device addresses: AD5593R 0x10, MPM54304 0x68, IDPROM 0x50 (CON1 only). (Address uniqueness is per-channel I²C segment; verify the microHAPS routes one channel segment at a time or that segments are isolated — see Open Item O-3.)
• Channel control GPIO (from AD5593R / microHAPS): CONx_EN/SYNCI (MPM enable), CONx_VCCO_EN, CONx_V12P0_EN, CONx_RESETn_HT3, CONx_PG (power-good).

6. Test Coverage Matrix (SOW → test cases)

Quality/MSA test cases (Trace TC-TS-001…006): coverage audit, measurement-uncertainty budget, calibration check, pass/fail review, GR&R, limit-derivation audit — applied to this spec before sign-off.

7. Detailed Test Cases

Each step runs per channel (CON1–CON5) unless stated. All steps are automated via the microHAPS HDL + TestStand sequence; results logged.

TC-PT-001 — Power Integrity & Protection

Objective: verify each channel's power chain powers up/down cleanly, rails are in limit, and protection responds. Setup: DUT on adapter; all channels initially disabled; PSU 12 V with current monitor. Procedure:

1. Apply 12 V; verify input presence and polarity (no reverse-current/fault); record idle current.
2. For CONx: assert CONx_V12P0_EN (eFuse on); confirm V12P0_SINK_CONx present; assert CONx_EN/SYNCI (MPM on).
3. Measure V3P3_CONx, V1P8_CONx, VCC_CONx via AD5593R ADC / test points; confirm within limits (§10).
4. Read CONx_PG (power-good) = asserted.
5. Disable channel; confirm rails decay and CONx_PG de-asserts (controlled power-down).
6. Protection: force an over-current/short condition (via Snowball-side controlled load on VCCO_CONx/V3P3_CONx if supported) and confirm eFuse/current-limit trips and recovers (no latch-up). (Load method = Open Item O-5.) Pass: all rails in limit on all 5 channels; PG correct; OCP trips & recovers; no unexpected fault. Pins: V12P0, V3P3_CONx, V1P8_CONx, VCC_CONx, CONx_PG, CONx_*_EN.

TC-PT-002 — I²C Accessibility & Device Identification + IDPROM

Objective: every I²C device responds at the correct address; IDPROM programmed & verified. Procedure:

1. With channel powered (V1P8/V3P3 up), run I²C scan on the channel segment via microHAPS.
2. Confirm AD5593R @ 0x10 and MPM54304 @ 0x68 ACK on every channel; IDPROM @ 0x50 ACKs on CON1 only.
3. Address-conflict check: no unexpected ACKs; B-side buffer segments isolate as designed.
4. R/W access: scratch read/write to AD5593R config; PMBus read of MPM (see TC-PT-006).
5. IDPROM (CON1): assert CON1_EEPROM_EN; program board name + SH number + identity fields per IDPROM Content Spec V2; read back and byte-compare. [content TBD from xlsx] Pass: all expected devices ACK at correct address per channel; IDPROM verifies byte-exact. Pins: I²C 0x10/0x68/0x50, CON1_EEPROM_EN.

TC-PT-003 — HT3/HT4 Interface Connectivity & At-Speed

Objective: verify each of the ~27 IO differential lanes per channel routes HT4↔HT3 correctly, at speed, with no opens/shorts/swaps. Setup: Snowball mated on HT3 (Jx); at-speed-capable HDL on microHAPS. (Signal flow HT4→HT3→Snowball: see Appendix C.) Procedure:

1. Continuity / open-short / swap: microHAPS drives a walking-1 / per-lane unique pattern on each CONx_IO_Lyy from HT4; Snowball captures at HT3 and reports (or loops back); verify 1:1 mapping, no stuck/shorted/swapped lanes, correct P/N polarity.
2. At-speed: run an at-speed pattern (PRBS) per lane at target rate [TBD rate]; verify BER/eye within limit through the panel routing.
3. Unused/unpowered connector handling: confirm a disabled/unpopulated channel does not back-drive or fault neighbours. Pass: all lanes pass continuity + at-speed on all 5 channels; correct polarity; no cross-channel interference. Pins: all CONx_IO_Lyy_[P/N] (27 pairs × 5 ch ≈ 270 IO signals) + the HT4 mirror — the bulk of pin coverage.

TC-PT-003b — HT3 Clocks

Objective: CLK0/CLK1 present and in spec at HT3. Procedure: microHAPS sources clock into the L25-derived CLK path → DS90LV001 LVDS buffers → CONx_CLK_[0/1]_[P/N]; Snowball measures presence and frequency. (Full per-channel signal path: see Appendix B.) Pass: both clocks present, frequency within [TBD], LVDS levels valid, on all channels. Pins: CONx_CLK_0_P/N, CONx_CLK_1_P/N.

TC-PT-004 — Voltage Negotiation (Vn_CONx)

Objective: verify the VCCO negotiation loop. Procedure:

1. Set DAC-controlled VMAX via AD5593R (I/O configured as DAC) per channel.
2. Drive cable-connected scenario (Snowball presents the VN/cable condition on HT3).
3. Measure Vn via AD5593R ADC inputs; verify correct Vn response.
4. Enable VCCO (CONx_VCCO_EN via VREF/level-shift path) and confirm VCCO_CONx does not exceed the negotiated limit. Pass: Vn tracks expected; VCCO ≤ negotiated VMAX on all channels. Pins: VN_CONx, VMAX_CONx, VREF_CONx, VCCO_CONx, CONx_VCCO_EN.

TC-PT-004b — Reset & Remote-Power Signaling

Objective: reset sequencing and remote-power behaviour correct end-to-end. Procedure: assert/deassert CONx_RESETn_HT3 from HT4 side (via PMF63UNE level-shift) and confirm at HT3 (Snowball); verify VREF→VCCO-enable interaction and any RMTPWRDn handling. Pass: reset reaches HT3 with correct polarity/sequence; VCCO-enable follows VREF as designed. Pins: CONx_RESETn_HT3, CONx_RESET_HT3, CONx_VCCO_EN.

TC-PT-005 — Telemetry & Thermal

Objective: ADC telemetry readable and sane; logged for records. Procedure: read AD5593R ADC channels for V3P3, VCCO, Vn, HT4 VREF (via the on-board dividers); read AD5593R integrated temperature; sanity-check ranges; log all to the production record. Pass: all telemetry within sane bounds; temp plausible; logged. Pins: AD5593R I/O0–I/O3 sense + temp.

TC-PT-006 — Power-Module (MPM54304) Configuration & Verify

Objective: PSM configured and verified. Procedure: over PMBus (0x68) write the MPM54304 configuration (output voltages incl. Buck3/4 direct-feed for VCCO per the design note, sequencing, current limits) [register set TBD from Design Log]; read back and verify; confirm resulting rails match TC-PT-001. Pass: MPM config read-back matches intended; rails correct. Pins: MPM 0x68.

TC-PT-007 — Golden-Unit Run & TestStand/Synplex Integration

Objective: full hands-off flow verified on a golden unit; released. Procedure: run the complete sequence end-to-end on a known-good unit; confirm TestStand sequence + Synplex integration produce the Golden Board Test Report; release in NextRelease for CM/Ops. Pass: golden unit PASS; report generated; released.

8. Pin Coverage Summary

This achieves "most pins + all functions": every powered net is exercised, the high-pin-count IO is covered lane-by-lane via the Snowball loopback, and each functional block has a dedicated test. Pins not directly stimulated (GND, decoupling, mechanical, no-connects) are covered structurally by power-up + continuity.

9. Production Test Flow (hands-off)

1. Operator loads DUT + Snowball(s) into fixture; scans serial.
2. Power-on & safety: TC-PT-001 idle current → channel-by-channel enable.
3. I²C bring-up & ID: TC-PT-002 (scan, addresses) → TC-PT-006 (MPM config) → IDPROM program/verify (CON1).
4. Connectivity & at-speed: TC-PT-003 + 003b (per channel; parallel if 5 Snowballs, else sequential).
5. Negotiation / reset / telemetry: TC-PT-004 + 004b + 005.
6. Power-down & verdict: controlled disable; aggregate logs; PASS/FAIL.

Channel strategy: 5 Snowballs → full parallel; 1–3 Snowballs (on hand) → sequential per channel with operator re-mate or indexed fixture (call out in Operator Instructions).

10. Limits (to be finalized — §7 readiness review)

11. Deliverables (SOW §5) — mapping

12. Acceptance Criteria (SOW §6)

Unit PASS iff: all PSM configured & verified · all IDPROMs programmed & verified · all power rails in limit · all I²C devices respond at correct addresses · all 5 channels pass functional tests · all clocks in spec · no unexpected over-current/latch-up/fault · logs show no unresolved warnings/errors. Any mandatory step failing = FAIL.

13. Open Items / Assumptions (SOW §7)

Appendix A — per-channel net reference (CON1; CON2–CON5 identical with index)

Power: V12P0, V12P0_SRC_CON1, V12P0_SINK_CON1, V3P3, V3P3_CON1, V3P3_CON1_F, V1P8_CON1, VCC_CON1, VCCO_CON1, VCCO_CON1T/F. I²C: CON1_SCL_IN/CON1_SDA_IN (A-side, pulled up) → _IN_V3P3, _IN_HT3, _EEPROM (B-sides). Control: CON1_EN/SYNCI, CON1_VCCO_EN, CON1_V12P0_EN, CON1_RESETn_HT3, CON1_PG, CON1_EEPROM_EN. Negotiation: VN_CON1, VMAX_CON1, VREF_CON1. Clocks: CON1_CLK0, CON1_CLK1 → CON1_CLK_[0/1]_[P/N]. IO: CON1_IO_L0..L26 [P/N] (HT4 ↔ HT3).

Appendix B — Representative clock signal path (CON2 CLK0)

How a channel's clock flows HT4 → panel → HT3 → Snowball → back (traced from the netlist; identical topology on all 5 channels — CON1 via U12/U13, CON2 via U36/U37). Path exercised by TC-PT-003b.

flowchart LR
    subgraph MH["microHAPS (test controller)"]
        MHC["CLK source + capture/verify"]
    end

    subgraph B12["B12-N_PB (DUT) — CON2 clock path"]
        direction TB
        JX2["JX2.D12 (HT4)<br/>CON2_IO_L25P_N8P2"]
        R60["R60 (0 Ω series)"]
        NODE["CON2_CLK0 node<br/>bias R9→VCCO_CON2 / R10→GND"]
        U36["U36 DS90LV001 LVDS<br/>VCC=V3P3_CON2, EN=U36_EN<br/>IN− ref R123/R124"]
        J2P["J2.117  CON2_CLK_0_P (HT3)"]
        J2N["J2.133  CON2_CLK_0_N (HT3)"]
        A0["HT3_A0_FP (HT3 IO)"]
        B0["HT3_B0_FP (HT3 IO)"]
        JX2 --> R60 --> NODE -->|pin3 IN+| U36
        U36 -->|"pin6 OUT+"| J2P
        U36 -->|"pin7 OUT−"| J2N
    end

    subgraph SNOW["Snowball (HT3 loopback board)"]
        SB["receive differential clocks;<br/>re-drive single-ended:<br/>CLK0 → A0, CLK1 → B0"]
    end

    MHC ==>|"HT4 (via adapter)"| JX2
    J2P -->|"HT3 diff"| SB
    J2N -->|"HT3 diff"| SB
    SB -->|"CLK0 single-ended"| A0
    SB -->|"CLK1 single-ended"| B0
    A0 -.->|"HT3 IO → HT4"| MHC
    B0 -.->|"HT3 IO → HT4"| MHC

Flow: clock in single-ended from HT4 (JX2.D12, lane L25) → R60 (0 Ω) → CON2_CLK0 (biased R9/R10) → DS90LV001 U36 IN+ (pin 3); IN− threshold from R123/R124 → U36 → LVDS CON2_CLK_0_P/N → HT3 J2.117/133 → Snowball. Note: node bias (R9/R10) and threshold (R123/R124) are referenced to VCCO_CON2 — clock slicing tracks the negotiated VCCO domain. Loopback (TC-PT-003b): Snowball loops the clocks back single-ended — CLK0 → HT3_A0_FP, CLK1 → HT3_B0_FP — returning via the HT3 IO → panel → HT4 → microHAPS capture. (CLK1 path mirrors via U37 → CON2_CLK_1_P/N.)

Appendix C — Signal flow HT4 → HT3 → Snowball (CON2 representative)

The B12-N panel is mostly a passive interposer for high-speed IO, with a few classes actively conditioned on-panel.

flowchart LR
    UHAPS["microHAPS (HT4)"] --> JX2["JX2 (HT4 connector)"]
    PSU["12 V — Accordion Plus PSU"] --> ME1["ME1 (12 V input terminal)"]

    subgraph PANEL["B12-N_PB — CON2"]
        direction TB
        IO["IO lanes L0–L24, L26<br/>DIRECT 1:1 trace (passive)"]
        L25["L25 lane<br/>pass-through (R59) + clock src (R60→U36)"]
        I2C["I²C: TCA9803 buffer A→B"]
        CLK["CLK0/1: DS90LV001 LVDS (App. B)"]
        RST["RESETn: PMF63UNE level-shift (Q25)"]
        PWR["POWER: V12P0 → TPS2595 eFuse → MPM54304 quad buck<br/>→ V3P3_CON2 (F4 PTC) + VCCO_CON2 (Q5 FET + F3 PTC)<br/>(12 V also → U18 LDO → global V3P3)"]
    end

    subgraph HT3["J2 (HT3 connector)"]
        direction TB
        J_IO["IO pins (L0P=J2.81, L1P=J2.74)"]
        J_CLK["CLK_0_P/N = J2.117 / J2.133"]
        J_I2C["SCL/SDA_IN_HT3"]
        J_RST["RESETn_HT3 = J2.145"]
        J_PWR["DUT power: V3P3_CON2_F = J2.1/3/5/7 · VCCO_CON2 · GND"]
    end

    JX2 --> IO --> J_IO
    JX2 --> L25 --> J_IO
    JX2 -->|"SCL/SDA_IN"| I2C --> J_I2C
    JX2 -->|"L25 → CLK"| CLK --> J_CLK
    JX2 -->|"VCCO-EN / VREF"| RST --> J_RST
    ME1 -->|V12P0| PWR --> J_PWR
    J_IO --> SNOW["Snowball (DUT on HT3)"]
    J_CLK --> SNOW
    J_I2C --> SNOW
    J_RST --> SNOW
    J_PWR --> SNOW

12 V is a board input, not a pass-through — it enters on ME1 and is regulated on-panel; the DUT only gets regulated 3.3 V + negotiated VCCO at HT3.

Appendix D — I²C bus split (CON2 representative)

The microHAPS I²C arrives as a single 1.81 V input bus that splits across parallel TCA9803 buffers into isolated, level-translated B-side segments. CON2–CON5 use two buffers; CON1 uses three (extra IDPROM branch).

flowchart LR
    UHAPS["microHAPS I²C (HT4)"] -->|"JX2.C4"| BUS["CON2_SCL_IN / SDA_IN<br/>input bus @ V1P8 (1.81 V)<br/>pull-ups R129/R130 → V1P8_CON2"]
    BUS -->|"A-side SCLA/SDAA (pin 2/3)"| U27["U27 TCA9803<br/>VCCA = V1P8 · VCCB = V3P3 (global)"]
    BUS -->|"A-side SCLA/SDAA (pin 2/3)"| U53["U53 TCA9803<br/>VCCA = V1P8 · VCCB = V3P3_CON2"]
    U27 -->|"B-side (pin 6/7) CON2_*_IN_V3P3 @ 3.3 V"| ONB["On-board:<br/>AD5593R U34 (0x10)<br/>MPM54304 U47 (0x68)"]
    U53 -->|"B-side (pin 6/7) CON2_*_IN_HT3 @ 3.3 V"| J2["J2 (HT3) → DUT / Snowball"]
    EE["(CON1 only) U23 → CON1_*_EEPROM<br/>M24C02 IDPROM (0x50)"]
    BUS -. "CON1 3rd branch" .-> EE

Buffers level-translate 1.81 V ↔ 3.3 V; each B-side has the TCA9803 integrated current source, so segments are isolated and carry no external pull-up by design.

Appendix E — Power distribution tree (two 12 V sources → regulators → VCCO)

Two independent 12 V inputs: (A) Accordion PSU → ME1, and (B) per-channel 12 V via the HT4 connector — electrically separate.

flowchart TB
    PSU["Accordion Plus PSU"] -->|12 V| ME1["ME1 terminal (SOURCE A)"]
    ME1 --> V12P0["V12P0 (global 12 V)"]
    HT4IN["HT4 connector JX(n).C2 (SOURCE B, per channel)"] --> V12SRC["V12P0_SRC_CONx (12 V)"]
    subgraph SRCA["Source A — V12P0 → on-board regulators"]
        direction TB
        V12P0 --> U18["U18 TLV766 LDO"] --> V3P3G["V3P3 (global 3.3 V)"]
        V12P0 --> MPM["MPM54304 x5 (PVIN)<br/>per-channel quad buck"]
        MPM --> V3P3C["V3P3_CONx (3.3 V)"]
        MPM --> VCCOG["VCCO_CONx (Buck3/4, negotiated)"]
        MPM --> VCCC["VCC_CONx (MPM internal LDO)"]
    end
    subgraph SRCB["Source B — V12P0_SRC_CONx (from HT4)"]
        direction TB
        V12SRC --> U19["TPS71501 LDO"] --> V1P8["V1P8_CONx (1.81 V) — I²C/logic"]
        V12SRC --> EFUSE["TPS2595 eFuse (CONx_V12P0_EN)"] --> SINK["V12P0_SINK_CONx"] --> HT4OUT["back to HT4 (JX(n).D2)"]
    end
    V3P3C --> FV3["PTC fuse"] --> V3P3F["V3P3_CONx_F"] --> J["HT3 (Jn) → DUT"]
    VCCOG --> QSW["RQ3E100 FET (VCCO_EN) + PTC"] --> VCCO["VCCO_CONx"] --> J
    V1P8 --> I2C["I²C A-side buffers + logic"]

• Source A (ME1) makes the DUT rails delivered on HT3 (V3P3_CONx, VCCO_CONx) + global 3.3 V.
• Source B (HT4 12 V) powers the per-channel 1.8 V LDO (I²C/logic) and is protected + returned to HT4 via the eFuse — does not itself reach HT3.
• 12 V never reaches HT3 — DUT gets only regulated 3.3 V + negotiated VCCO.
• O-10: channel V1P8/I²C depends on Source B (HT4 12 V); the rig must supply 12 V on HT4 in addition to the Accordion PSU on ME1.

Appendix F — HT3x2-HT4x2 Adapter (SH100008643) block schematic

The adapter (ETT00000014, Probe board 29) is active — it level-translates I²C, expands GPIO for power control, generates/gates the HT4 12 V, and carries ID EEPROMs. One channel shown (board is ×2).

flowchart LR
    subgraph MH["microHAPS side (HT3 SEAF + SEAM-20)"]
        MH_I2C["I²C @ 3.3 V SCL/SDA"]
        MH_IO["high-speed IO lanes"]
        MH_PWR["supply in (12 V / rails)"]
    end
    subgraph ADP["HT3x2-HT4x2 Adapter — per channel (×2)"]
        direction TB
        EXP["TCA9555 (U9/U12)<br/>I²C GPIO expander<br/>power ctrl + HT4-ID read"]
        EE["EEPROMs 24AA024H (U1/U4)<br/>M24C02 (U8/U11) — ID"]
        PCA["PCA9306 (U7/U10)<br/>I²C level translate 3.3 V ⇄ 1.8 V"]
        BOOST["MP3431 boost + eFuse<br/>→ P12V_HT4_OUT (EN/FLT gated)"]
        LDO["TPS715 LDO / rails → P1V8, P3V3"]
    end
    subgraph DUT["DUT side — HT4 / APF6 (J1/J2)"]
        DUT_I2C["HT4 I²C @ 1.8 V"]
        DUT_PWR["HT4 power 12 V + 1.8 V"]
        DUT_CTL["HT4_ID0-4 · RMTPWRD_N · P12V_EN/FLT"]
        DUT_IO["HT4 IO lanes"]
    end
    MH_I2C -->|"I²C 3.3 V"| EXP
    MH_I2C -->|"I²C 3.3 V"| EE
    MH_I2C -->|"I²C 3.3 V"| PCA
    PCA -->|"I²C 1.8 V (HT4_SCL/SDA_OUT_R)"| DUT_I2C
    EXP -->|"P12V_HT4_OUT_EN"| BOOST
    BOOST -.->|"P12V_HT4_OUT_FLT"| EXP
    EXP <-->|"RMTPWRD_N / HT4_ID0-4"| DUT_CTL
    MH_IO ===|"IO lanes (routed SEAF⇄APF6)"| DUT_IO
    MH_PWR --> BOOST
    MH_PWR --> LDO
    BOOST ==>|"12 V"| DUT_PWR
    LDO ==>|"1.8 V"| DUT_PWR
    LDO -.->|"1.8 V VREF"| PCA
    LDO -->|"3.3 V"| EXP
    LDO -->|"3.3 V"| EE

• I²C: microHAPS-side 3.3 V (TCA9555 + ID EEPROMs); PCA9306 translates to 1.8 V for the DUT's HT4 — why the B12-N sees 1.8 V I²C on HT4.
• Power: adapter generates/gates the HT4 12 V (MP3431 boost + eFuse, TCA9555 EN/FLT) + 1.8 V/3.3 V — i.e. the B12-N's V12P0_SRC_CONx (O-10 "Source B") originates here.
• Control: TCA9555 reads HT4_ID0-4 and drives RMTPWRD_N + 12 V enable — the "power control is critical" path (E-004).
• High-speed IO routing on the adapter not yet individually traced; not yet schematic-confirmed.

Appendix G — I²C device address map (full stack)

Every I²C device microHAPS → adapter → B12-N, with its 7-bit address. ✅ confirmed; ⚠️ strap/logic-dependent.

flowchart TB
    M["microHAPS I²C master"]
    subgraph ADP["HT3x2-HT4x2 Adapter (per channel ×2)"]
        direction TB
        EXP["TCA9555 GPIO expander<br/>0x20–0x27 ⚠️ (A0-2 strap)"]
        EE1["24AA024H / AT24C02C<br/>0x50–0x57 ⚠️ (A0/A1 set by SN74LVC1G04 U2/U3, A2 strap)"]
        PCA["PCA9306 — translate 3.3 V ⇄ 1.8 V (no addr)"]
        EE2["M24C02 (U8/U11)<br/>0x50 / 0x57 ⚠️ (E0-2 commoned, strap R90)"]
    end
    subgraph B12["B12-N DUT (per channel ×5, behind TCA9803 buffers)"]
        direction TB
        BUF["TCA9803 buffers (1.8 V ⇄ 3.3 V, isolating)"]
        AD["AD5593R — 0x10 ✅"]
        MPM["MPM54304 — 0x68 ✅"]
        IDP["M24C02 IDPROM — 0x50 ✅ (CON1 only)"]
    end
    M -->|"I²C 3.3 V"| EXP
    M -->|"I²C 3.3 V"| EE1
    M -->|"I²C 3.3 V"| PCA
    PCA -->|"I²C 1.8 V"| EE2
    PCA -->|"I²C 1.8 V (→ B12-N HT4)"| BUF
    BUF --> AD
    BUF --> MPM
    BUF --> IDP

⚠️ NO I²C multiplexer/switch anywhere in the chain (verified vs both BOMs; PCA9306 is a level translator, TCA9803 a transparent repeater). De-confliction is by bus separation + strap addressing:

• Channel-to-channel (5× 0x10/0x68/0x50): each channel is a physically separate I²C bus (CONx_SCL/SDA per HT4). Channel selection is upstream on the microHAPS (FPGA masters or a mux on the microHAPS board — ETT00000008, not yet reviewed).
• Within a channel — real 0x50 conflict risk: adapter M24C02 (≈0x50) shares the 1.8 V HT4 bus with the B12-N IDPROM (0x50) through the always-on transparent TCA9803 → they can collide unless strap addresses differ. The inverter-driven 24AA024H address looks like a deliberate de-confliction scheme — confirm resolved per-channel addresses (→ O-3).

B12-N_PB — Production Test Specification (ALT: Loopback / no-microHAPS)

DUT: B12-N Panel Board (B12-N_PB, SH100008620) Approach: No microHAPS, no HT3-HT4 adapters. Snowball on HT3 + fully passive loopback plugs on HT4 + an external I²C selector/driver box + Accordion Plus. Status: DRAFT v0.2 · on-disk master docs/b12n-ht3/B12-N_PB_Test_Spec_ALT-Loopback.md; board detail = HT4_Loopback_Board_Design_Spec.md. Scope: at-speed OUT of scope; clocks via a passive Snowball-driven functional loopback; reduced IO fault-isolation accepted. v0.2 change: the HT4 plug is now fully passive — all I²C select/level-shift/drive moves to the external selector box; the on-plug AD5593R/DAC is removed. Clocks are Snowball-driven (passive routing); V12P0_SINK is shown on a plug LED and read by Snowball on a status lane. Source B is fed 12 V from the rig PSU (no 3.3 V rail).

1. Purpose & Scope

Complete, automated, hands-off production test for every B12-N_PB unit using a drastically simplified rig — power, IO connectivity, I²C accessibility, clock buffers, voltage negotiation, telemetry, reset/remote-power, and board identity across all 5 channels with no operator cable-moves. Out of scope: at-speed (microHAPS spec / Phase C), system/board validation, repair, firmware beyond test enablement.

2. Device Under Test (summary)

HT3-to-HT4 panel, 5 channels (CON1–CON5). Per channel: MPM54304 quad buck (0x68), TPS71501 LDO (V1P8), TPS2595 12 V eFuse, RQ3E100 VCCO switch, AD5593R monitor (0x10) — the DUT's own ADC/DAC/GPIO sensing rails/VN/VMAX + control GPIO, TSV631 Vn-negotiation, 2–3× TCA9803 I²C buffers, 2× DS90LV001 LVDS clock buffers, PMF63UNE level-shifters, LED; CON1 also M24C02 IDPROM (0x50). Two power inputs: ME1 = 12 V (Source A → regulators) and HT4 V12P0_SRC (Source B → V1P8/eFuse) — fed 12 V from the rig PSU (eFuse/LDO are native 12 V). No 3.3 V rail (Appendix E.3).

3. Test Architecture & Topology

flowchart TB
    ACC["Accordion Plus (Linux) - I2C master + GP[2:0] + 12 V PSU + Power GND"]
    BOX["Selector/driver box - GP[2:0] to 1-of-5 I2C select; 3.3 to 1.8 V level-shift; pull-ups (I2C only)"]
    subgraph PLUGS["5x passive HT4 plugs (no ICs)"]
        LBP["loopback shorts; clock route to L25; V12P0_SINK clamp+LED+status lane"]
    end
    subgraph DUT["B12-N_PB (DUT) per channel x5"]
        direction TB
        HT4["HT4 (JXn)"]
        PANEL["panel: IO pass-through HT4<->HT3; I2C buffered HT4->HT3 (TCA9803); on-panel AD5593R 0x10 / MPM 0x68 / IDPROM 0x50; CLK via LVDS (one-way)"]
        HT3["HT3 (Jn)"]
        HT4 --- PANEL --- HT3
    end
    SNOW["Snowball on HT3 - IO + clock drive/capture; I2C control target"]
    ACC <==>|"I2C(3.3V) + GP[2:0]"| BOX
    ACC ==>|"12 V PSU + GND to ME1 + plugs V12P0_SRC"| DUT
    BOX <==>|"selected I2C(1.8V) + GND; 3-pin, 5 identical cables (star)"| LBP
    LBP -->|"I2C(1.8V) to HT4; 12 V to V12P0_SRC"| HT4
    LBP <-->|"HT4 IO loopback shorts"| HT4
    HT3 <-->|"IO + clock drive/capture"| SNOW
    HT4 -.->|"I2C to panel to HT3 (control ch.)"| HT3
    HT3 -.->|"I2C control channel + SINK status"| SNOW

• IO test loop: Snowball drives an HT3 lane -> panel -> HT4 -> plug shorts to a paired HT4 lane -> panel -> HT3 -> Snowball reads (Appendix E.4).
• I²C control channel: the selected channel's I²C reaches Snowball through the DUT (HT4 -> TCA9803 -> HT3), so commanding Snowball also exercises the HT3-side I²C buffer; the same I²C reaches the DUT AD5593R 0x10 / MPM 0x68 / IDPROM 0x50.
• Clock & SINK: Snowball drives the clock on a dedicated loop lane -> routed on the plug to L25 -> DUT LVDS -> Snowball reads CLK0/1 at HT3. V12P0_SINK clamped on the plug (LED) + routed onto a status lane -> HT3 -> Snowball.

Roles: Accordion = I²C master + GP[2:0] + 12 V PSU + Power GND. Selector box = the only active test hardware (1-of-5 I²C select, 3.3<->1.8 V level-shift, pull-ups; I²C only, no power). 12 V is a separate PSU harness -> ME1 + each plug's V12P0_SRC. HT4 plug = fully passive (loopback shorts + clock route + SINK clamp/LED/status lane). Snowball = IO + clock drive/capture + I²C control target.

4. Test Equipment & Fixtures

No microHAPS. No HT3-HT4 adapters. No active parts on the plugs.

5. Test Access Map

• I²C: Accordion (3.3 V) + GP[2:0] -> box picks 1 of 5, level-shifts to 1.8 V, presents the selected channel's I²C on that plug's cable -> DUT CONx_SCL/SDA_IN -> TCA9803 -> AD5593R 0x10 / MPM 0x68 / IDPROM 0x50 + Snowball. Only the selected channel is live -> no address collision.
• Power: one 12 V PSU feeds ME1 (Source A) and each plug's V12P0_SRC (Source B) via a separate harness — not the signal connector, not the box. No 3.3 V rail. Sequence: 12 V -> V1P8 -> I²C.
• IO: Snowball drives/reads HT3; the passive plug loops lanes back (E.4).
• Clocks: Snowball drives a loop lane (HT3, at VCCO) -> panel -> HT4 -> plug routes to L25P/L25N -> DUT DS90LV001 -> CLK0/1 at HT3 -> Snowball reads (Appendix D).
• SINK/presence: SINK clamped on the plug -> LED + status lane -> HT3 -> Snowball. Presence = I²C ACK.
• Channel control/rails: via the DUT AD5593R 0x10 (CONx_VCCO_EN, reset, rail ADC), MPM enable, CONx_V12P0_EN (reachability per O-L3).

6. DUT functional blocks to test

Per channel (×5; CON1 also IDPROM):

7. Coverage Matrix (SOW -> TC)

8. Detailed Test Cases

All from the Accordion (TestStand); channel select by the box (GP[2:0]); no operator cable-move.

TC-L-001 Power Integrity & Protection — Setup: channels disabled; 12 V PSU to ME1 + plugs' V12P0_SRC. (1) apply power, idle current, no fault; (2) assert CONx_V12P0_EN -> confirm SINK up via plug status lane (LED + Snowball); assert CONx_EN/SYNCI; (3) read V3P3/V1P8/VCC via DUT AD5593R; (4) read PG/FLT via DUT AD5593R GPIO (O-L3); (5) disable, rails decay + SINK LED off; (6) over-current via Snowball load -> eFuse trips & recovers. Pass: rails in limit all 5; PG/SINK/OCP correct.

TC-L-002 I²C Accessibility, Control Channel & IDPROM — select channel; scan -> AD5593R 0x10 + MPM 0x68 ACK; IDPROM 0x50 on CON1 only; no unexpected ACKs (only selected channel live). Reach Snowball over I²C through the DUT (= HT3 buffer + presence). AD5593R scratch R/W; MPM PMBus read. IDPROM program + byte-compare (CON1).

TC-L-003 HT3/HT4 IO Connectivity (loopback) — Snowball walking-1 per HT3 lane -> panel -> HT4 -> plug short -> back -> Snowball (E.4 map). Verify 1:1, no opens/shorts/swaps, P/N polarity. Disabled channel doesn't back-drive. (Per-lane isolation reduced — accepted. At-speed not performed.)

TC-L-003b HT3 Clocks (passive functional loopback) — Snowball drives the driver lane differentially (at VCCO, same VCCO both sides) -> panel -> HT4 -> plug route -> L25P (CLK0)/L25N (CLK1) -> DUT DS90LV001 slice around VCCO/2 -> LVDS at HT3 -> Snowball reads both. Pass: both clocks toggle cleanly (functional toggle, not DC-threshold — Appendix D).

TC-L-004 Vn — DUT AD5593R DAC VMAX; present cable scenario; measure Vn via ADC; enable VCCO; confirm VCCO <= negotiated VMAX. TC-L-004b Reset/Remote-Power — drive RESETn_HT3/VCCO_EN via DUT AD5593R GPIO; observe at HT3 via Snowball. TC-L-005 Telemetry — DUT AD5593R ADC V3P3/VCCO/Vn/VREF + temp; log. TC-L-006 MPM config — PMBus 0x68 write+readback; rails match TC-L-001. TC-L-007 Golden unit — full flow all 5 channels; TestStand+Synplex report; release.

9. Pin Coverage Summary

HT3<->HT4 IO ~27 pr/ch (~270) via TC-L-003 (12 pairs + 3 special lanes, E.4); clocks CLK0/1 via TC-L-003b; I²C via TC-L-002 (box select + control channel); power/PG/SINK via TC-L-001/006 (DUT AD5593R + PMBus + status lane); negotiation/telemetry TC-L-004/005; reset TC-L-004b; sideband = O-L2. The 3 special lanes (clock-driver, L25, status) are tested functionally (clock toggles / SINK reads), not by walking loopback (O-L6).

10. Production Test Flow

Load DUT + 5 passive plugs + Snowball(s); scan serial (one load, no cable-moves). Power-on/safety (TC-L-001) -> I²C & ID (TC-L-002 -> 006 -> IDPROM) -> connectivity & clocks (TC-L-003 + 003b) -> negotiation/reset/telemetry (004/004b/005) -> power-down & verdict. Sequential via box select (one Snowball indexed) or parallel with 5 Snowballs — operator never moves a cable.

11. Limits (to finalize)

12 V Source A (ME1) 12.0 [TBD]; 12 V Source B (V12P0_SRC) 12.0 [TBD]; V3P3 3.3 [TBD]; V1P8 1.81 [TBD]; VCCO negotiated <= VMAX [TBD]; channel current [TBD]; CLK0/1 frequency [TBD]; AD5593R temp [TBD].

12. Deliverables

This spec · board spec (HT4_Loopback_Board_Design_Spec.md) · scripts (Accordion/TestStand + Snowball) · fixture (5× passive plug + 1 selector/driver box) + BOM · coverage matrix · Golden Board Test Report · Release Note · Operator Instructions.

13. Acceptance Criteria

PASS iff (SOW §6, at-speed excluded): PSM configured+verified · IDPROMs programmed+verified · rails in limit · all I²C ACK at correct addresses (all 5, via box select) · all 5 pass IO loopback · both clocks toggle in spec · SINK/OCP correct · no over-current/latch-up/fault · logs clean. Any mandatory fail = FAIL.

14. Open Items

• O-L1 numeric limits.
• O-L2 HT3 sideband coverage (UMRIN/UMROUT/IDC/IDD/IDA/RSB).
• O-L3 confirm PG/FLT, VCCO_EN, reset, V12P0_EN reachable via DUT AD5593R 0x10 (traces on board 28).
• O-L4 OCP/short-injection (Snowball load).
• O-L5 Snowball capacity (drive+capture ~27 IO pr/ch, drive clock driver lane at VCCO, read CLK0/1).
• O-L6 3 special lanes tested functionally — accept or add check.
• O-L7 selector/driver box design (TCA9548A vs 74HC138+switches; level-shift; pull-ups; I²C only, no power; 5 plug 3-pin cables).
• O-L8 passive plug design (HT4_Loopback_Board_Design_Spec.md).
• O-L9 12 V PSU -> ME1 + plugs' V12P0_SRC, separate harness; sequence 12 V -> V1P8 -> I²C.
• O-L10 confirm Snowball driver lane crosses VCCO/2 by >±100 mV at max VCCO; Source B = 12 V native.

Appendix A — Comparison vs microHAPS

Headline: DUT has 5 HT4 connectors but microHAPS+adapter exposes only 4 -> operator must move an HT4 cable mid-test for ch.5. The loopback alt fits a passive plug on every HT4 (5×) -> all 5 at once, no cable-move.

• Test/methodology: original sources/captures from HT4, manual cable-move for ch.5, at-speed possible · alt = passive plug on all 5 + Snowball, hands-off, functional-loopback clocks, no at-speed.
• Hardware: original = costly SNPS-gated microHAPS + active adapters · alt = 5 passive plugs + 1 selector/driver box + Accordion + Snowball.
• Software: original = FPGA HDL + no-mux (O-3 open) + cable-move pause · alt = Accordion I²C + box GP[2:0] select (O-3 solved) + Snowball over I²C-through-DUT, no FPGA HDL.

Appendix C — I²C address map (with box select)

Per channel (box-selected via GP[2:0]) the live bus carries DUT AD5593R 0x10, MPM 0x68, IDPROM 0x50 (CON1) + Snowball (control + presence ACK). The box presents one channel at a time -> repeated 0x10/0x68/0x50 never collide (O-3 solved). No adapter devices (plug is passive) — only 0x10 on a live channel is the DUT's own.

Appendix D — Clock test (passive functional loopback)

L25P->CLK0 (U36), L25N->CLK1 (U37): two single-ended DS90LV001, each vs its own VCCO/2 ref (R9/R10, R11/R12 = 100 ohm termination; R123/R124 = 10k threshold). Instead of a DC sweep (a weak source can't drive the 50 ohm termination), Snowball drives a real toggle: driver lane (HT3) -> panel -> HT4 -> plug routes onto L25P/L25N -> DUT slices around VCCO/2 -> LVDS at HT3 -> Snowball reads. A push-pull driver easily drives the 50 ohm-to-VCCO/2 load; Snowball is referenced to the same VCCO so high/low straddle VCCO/2 across the VCCO range. Functional toggle/frequency test (matches SOW), not DC-threshold; no on-plug DAC/op-amp/LVDS. Confirm Snowball crosses VCCO/2 by >±100 mV at max VCCO (O-L10).

Appendix E — HT4 loopback plug (fully passive) + selector box

Plug = passive interposer (no ICs): connectors + PCB loopback shorts + a V12P0_SINK clamp/LED/status route. Active functions in the external selector/driver box. Board detail: HT4_Loopback_Board_Design_Spec.md.

E.1 Plug signal connector + power

Signal connector = 3-pin single-row header SCL · SDA · GND (box does select + level-shift; plug passes through to HT4): SCL = CON2_SCL_IN C4 (1.8 V); SDA = CON2_SDA_IN C6 (1.8 V); GND = I²C return to box. Power (separate feed): 12 V PSU + Power GND -> DUT ME1 (Source A) and each plug's V12P0_SRC (C2, Source B = 12 V) via a robust harness; plug routes 12 V to C2. Not on the signal connector; no 3.3 V rail. SINK + clock are not on either connector — SINK returns to Snowball on the status lane; clock is Snowball-driven via the driver lane. I²C pull-ups in the box (1.8 V plug side); DUT keeps R129/R130 -> V1P8. Geometry (JX2/JX4 tightest): plug can't grow on its short edge -> the 3-pin signal header sits on a long edge (fine pitch); 12 V power is a separate non-space-critical feed. (2-pin SCL·SDA only if a solid common GND serves as the I²C return.)

E.2 Plug contents (passive)

IO loopback (PCB/0 ohm, 12 pairs); clock route (driver-lane HT4 pins -> L25P/L25N); SINK clamp + LED (R + clamp diode + LED, 12 V -> logic level); status route (clamped SINK -> status-lane HT4 pin -> HT3); connectors (APF6 HT4 + 3-pin signal header + 12 V power input). No active devices.

E.3 Source B voltage (we use 12 V)

The rig has a 12 V PSU and no 3.3 V rail, so Source B (V12P0_SRC) is fed 12 V (native). On the DUT it drives only U19 TPS71501 LDO -> V1P8, and U14 TPS259540 eFuse -> V12P0_SINK (so SINK ~ 12 V; the plug divides/clamps to a logic level for LED + status lane). Flexibility note: both parts also work at ~2.7–3.3 V (eFuse 2.7–18 V, logic-enabled, no 12 V UVLO), so 3.3 V would also work — but no reason to add a 3.3 V rail.

E.4 HT4 IO lane allocation (27 lanes / 54 pins)

27 differential lanes L0–L26. Allocation: 12 loopback pairs (24 lanes) plug shorts P->P, N->N; 1 clock-driver lane L12 -> L25 (L12_P->L25P D12, L12_N->L25N C12; Snowball drives L12, both clocks toggle); L25 (D12/C12) clock inputs (driven by L12); 1 status lane L26 (clamped SINK -> L26_P C8; L26_N C10 = FLT/plug-ID strap or GND). Ground-interleaved connector; the 12 pairs use a half-connector offset so adjacent lanes never share a loop.

Loop pairs: L0(F2/F4)<->L13(E6/E8); L1(F6/F8)<->L14(E10/E12); L2(F10/F12)<->L15(B10/B12); L3(A10/A12)<->L16(B6/B8); L4(A6/A8)<->L17(B2/B4); L5(A2/A4)<->L18(E22/E24); L6(F22/F24)<->L19(E18/E20); L7(F18/F20)<->L20(E14/E16); L8(F14/F16)<->L21(B14/B16); L9(A14/A16)<->L22(B18/B20); L10(A18/A20)<->L23(B22/B24); L11(A22/A24)<->L24(D8/D10). Special: L12(E2/E4)->clock driver -> L25(D12/C12); L26(C8/C10)=status (clamped SINK + FLT/strap -> HT3).

Tally: 24 (12 pairs) + 1 (L12) + 1 (L25) + 1 (L26) = 27 lanes / 54 pins — all matched, nothing floating. Plug netlist ~28 passive connections (24 loop shorts + 2 clock-route + ~2 status) + the SINK clamp/LED. Pin-based map identical for all 5 plugs (one passive design ×5); verify per-channel net->pin on CON1/3/4/5 before fab.

HT4 Loopback Plug — Design Specification

Passive interposer that mates one DUT HT4 connector; 5 identical plugs per DUT. Connectors and copper only — no active devices. Used by the loopback test spec (E-032). Pin-level map: B12N_HT4-DUT-HT3-Snowball_map.csv.

Block schema

flowchart LR
  subgraph RIG["Test rig"]
    ACC["Accordion Plus<br/>I2C master · GP[2:0] · PSU (3V3/5V Source B)"]
    BOX["Selector/driver box<br/>1-of-5 I2C select · 3.3<->1.8 V · pull-ups · Source B"]
    SNOW["Snowball (on HT3)<br/>IO + clock drive/capture"]
  end
  subgraph DUT["B12-N DUT — per channel x5"]
    HT3C["HT3 conn (Jn)"]
    PANEL["Panel<br/>IO pass-through · TCA9803 I2C buffer · DS90LV001 clock buffers<br/>eFuse -> V12P0_SINK · AD5593R 0x10 (ADC reads VREF)"]
    HT4C["HT4 conn (JXn)"]
    HT3C --- PANEL --- HT4C
  end
  subgraph PLUG["HT4 Loopback Plug — passive"]
    HDR["4-pin header<br/>SCL · SDA · GND · VSRC"]
    FOLD["IO fold shorts<br/>Ax<->Fx · Bx<->Ex · Cx<->Dx (12 pairs)"]
    CLK["Clock<br/>L12 -> L25P/L25N -> CLK0/CLK1"]
    SV["SINK->VREF tie<br/>D2 -> D24"]
  end
  ACC <-->|"I2C 3.3 V + GP[2:0]"| BOX
  BOX <==>|"4-pin: I2C 1.8 V + Source B"| HDR
  HDR -->|"VSRC -> C2 · SCL/SDA -> C4/C6"| HT4C
  SNOW <-->|"IO lanes + clock lane"| HT3C
  FOLD -->|"P->P / N->N folds"| HT4C
  CLK -->|"L25P/N -> DS90LV001 -> CLK0/CLK1 -> HT3"| SNOW
  HT4C -->|"V12P0_SINK (D2)"| SV
  SV -->|"VREF (D24)"| HT4C
  HT4C -.->|"AD5593R 0x10 ADC reads VREF -> eFuse-OK over I2C"| BOX

Connectors

Power (Source B)

P-HDR.VSRC -> HT4 C2 (V12P0_SRC), 3V3 or 5V; P-HDR.GND -> GND (shared return). On the DUT, Source B feeds the eFuse (-> V12P0_SINK) and the V1P8 LDO.

I2C

P-HDR.SCL -> HT4 C4 (CONn_SCL_IN); P-HDR.SDA -> C6. 1.8 V; pull-ups and 3.3<->1.8 V level-shift live in the box.

eFuse status (SINK -> VREF)

Plug ties HT4 D2 (V12P0_SINK) -> HT4 D24 (VREF) with a direct copper trace. The DUT AD5593R (0x10) reads VREF over I2C: VREF ~ Source B => eFuse passing; VREF ~ 0 => not passing.

IO loopback shorts — 12 differential pairs (copper, P->P / N->N)

• A<->F: A2-F2 · A4-F4 · A6-F6 · A8-F8 · A10-F10 · A12-F12 · A14-F14 · A16-F16 · A18-F18 · A20-F20 · A22-F22 · A24-F24
• B<->E: B6-E6 · B8-E8 · B10-E10 · B12-E12 · B14-E14 · B16-E16 · B18-E18 · B20-E20 · B22-E22 · B24-E24
• C<->D: C8-D8 · C10-D10
• B2/B4 (L17): spare, no-connect.

Clock (L25 -> CLK0/CLK1)

HT4 D12 = L25P -> CLK0 (U36) and C12 = L25N -> CLK1 (U37) are independent single-ended DUT clock inputs. The plug routes the Snowball-driven L12 lane onto them: E2 -> D12 (CLK0) and E4 -> C12 (CLK1). The DUT DS90LV001 buffers present CLK0/CLK1 at HT3, where Snowball reads them.

Plug BOM

APF6 / ASP-229938 mate · 4-pin header · copper / 0 ohm loopback shorts · D2->D24 copper tie · optional ESD.

Phase A prerequisites (from the 2026-06-03 Mathias Svensson meeting). Status update 2026-06-04:

• ✅ MicroHAPS R0 board — on hand (enables platform bring-up / smoke test, MS-002).
• ✅ Technical contact — Erik Ingemarsson (Synopsys HW Eng) acting as the technical contact.
• ⏳ Snowball units — still required; gate the B12-N DUT test implementation (MS-003+).
• ⏳ HT3→HT4 adapter (SH100008643) — still required; gate the B12-N test steps.

Remaining hard blockers: Snowball units + HT3→HT4 adapter (SNPS to provide per the signed SOW, which commits SNPS to supply required HAPS hardware). Note: the basic smoke test (MS-002) can proceed now with the R0 board + host environment; the Snowball/adapter only gate the actual B12-N test implementation (MS-003 onward).

All components (Micro-HAPS, A2, PC, power) must be placed in CAD and mechanical fit confirmed — no clashes, all connectors and cable routes accessible. Close this when done.

Progress

• 2026-06-15: 3D PDF klar och akryl utskuren. Prototyp byggs klart.
• 2026-06-19: 3D-modell klar.

3D PDF must be exported from CAD and shared with relevant stakeholders for review. Close this when done.

Acrylic fixture plate must be cut in-house and confirmed to fit the fixture frame. Close this when done.

After receiving the SOW + associated docs (via Johan Aasa) and consulting Logan Seitz (mechanical), Erik Ingemarsson (microHAPS), and Per Ekelund (benchtop tester), Daniel's understanding was corrected — earlier assumptions about E# scope were wrong. Dave Upton confirmed: "you are now aligned."

Current status (DU-confirmed):

• Hardware test solution finalized / very close — pending mech verification together with the B12-N HT3 board is underway (subject to the enclosure/review points below).
• HDL done — HCI design with GPIO expander + I2C master endpoints. Additionally, SSTDM HDL enables at-speed testing and will run on some assemblies.
• microHAPS R1 tape-out done — major change relates to FTDI and power-input control (see technical-corrections notice — power control is in fact critical).
• Test adapter board (HT3X2-HT4X2 adapter) designed; being assembled now.
• Test methodology: some tests (e.g. MPS regulator programming) currently run on a benchtop tester the Lund team set up — but this is interim only (see notice).

Deployment: for the June 2026 deployment, Synopsys provides the microHAPS + fixture hardware directly for the B12-N HT3 Panel Board.

Rationale for capturing: Daniel explicitly wants to avoid repeating an earlier scoping mistake; this records the agreed baseline so remaining E# tasks (see milestone MS-001) are scoped against a correct status. Key contacts: Dave Upton (SNPS, board owner), Johan Aasa, Logan Seitz (mech), Erik Ingemarsson (microHAPS), Per Ekelund (benchtop), Synplex (release target), Ops.

Synopsys delivered the Statement of Work — "Production Test Development and Execution for B12-N_PB" (file: docs/b12n-ht3/Production Test SOW for B12-N_PB.docx; last modified by Vic Juneja, 2026-05-21; review comments by Johan Aasa). It is the governing scope document for this project.

Purpose: ensure every manufactured B12-N_PB (SH100008620) unit meets functional, electrical, and interface requirements before integration/shipment — validating power, I/O connectivity, I2C accessibility, HT3/HT4 behaviour, telemetry, and board identity, per the B12-N_PB Implementation Specification.

In scope (§2.1): production test strategy & flow (automated, hands-off); test HW definition (HT4-side access as primary control interface; microHAPS + HT3x2-HT4x2 adapter + Snowball); SW/automation fully integrated with TestStand + Synplex; electrical/functional coverage (power integrity & protection, connector power up/down, HT3/HT4 at-speed, HT3 clocks, I2C accessibility & addressing, VCCO negotiation, reset & remote-power signalling, power-module configuration, IDPROM programming); documentation & handoff; verified on golden unit; released in NextRelease for CM/Ops.

Out of scope (§2.2): system/board validation & characterization; repair procedures; firmware feature development beyond test enablement (unless added via amendment).

Deliverables (§5): Production Test Specification; Automated Test Scripts; Test fixture & accessories + their BOM; Test Coverage Matrix; Golden Board Test Report; Release Note; Operator Instructions (if applicable).

Acceptance (§6): PASS when all PSM configured & verified, all IDPROMs programmed & verified, all power rails within limits, all I2C devices respond at correct addresses, all five channels pass, all clocks in spec, no over-current/latch-up/fault, and logs show no unresolved warnings/errors. Failure of any mandatory step = FAIL.

Test requirements captured as REQ-PT-001…007; deliverables/tasks tracked under milestone MS-001 (June 2026 deployment). See related notices for part-number reconciliation, IDPROM review comments, and assumptions/change-management.

E-Sharp AB issued "B12N-HT3 Panel Test Station — Quote and Proposal (May 2026)" (docs/b12n-ht3/B12N-HT3 Panel Test Station Quote and Proposal – May 2026.docx; author Gustav Kihlberg, last modified Daniel Hansson; 2026-05-07/08) as the commercial response to the Synopsys Production Test SOW (decision E-005).

Offer: deliver a lab-based test station for the B12N-HT3 front panel using Synopsys-provided hardware, with E# developing and integrating the test software.

Commercials: ~160 engineering hours, ~SEK 240,000 at standard E# rates. Target: June 2026 (subject to HW readiness & the stated assumptions). Effort split: Snowball test development ~60 h; TestStand sequence + Synplex integration ~40 h; lab station assembly + reproduction prep ~40 h; coordination & technical follow-up ~20 h.

Deliverables: D1 Snowball Test Suite (adapted to B12N-HT3 topology); D2 TestStand Sequence (test steps + operator instructions); D3 Synplex Integration (release artefacts); D4 Lab Test Station (assembled, integrated, verified via bring-up/sanity at the E# lab).

In scope (E#): adapt/implement the Snowball suite; develop the TestStand sequence; integrate into Synplex; prepare for formal release; assemble the lab station from SNPS-provided HW (microHAPS, fixturing, PSUs, accessories); system-level integration (DUT/fixture/Snowball/software); basic bring-up, sanity checks, verification at the E# lab; reproduction prep (receive BOM & supply channels, write assembly instructions).

Plan phases: (1) System Integration & Test Development; (2) System Validation (bring-up at E# lab); (3) Finalisation & Handover.

Important: this quote deliberately narrows scope vs the SOW — see the scope-delta notice. Aligns with milestone MS-001 (June 2026).

Meeting notes sent by Daniel Hansson (E#, Deputy CEO & Business Development Director) to Mathias Svensson (business responsible, Synopsys), 2026-06-03 — sent for confirmation/feedback (pending SNPS confirmation). Covered scope, prerequisites, and commercial setup for the Micro HAPS projects, focusing on Phase A with initial planning for B and C.

Phase A — scope & timeline: to be delivered within July 2026. Limited to software development & integration:

• Snowball test development
• TestStand sequence development
• Synplex integration
• Project coordination & technical follow-up

No mechanical changes to the Micro HAPS chassis; the existing Micro HAPS PCBa R0 is used.

Commercial model: hourly basis; estimated 120 hours at the Principal Engineer rate → ≈ SEK 270,000.

Relationship to prior quote: this revises the May quote (E-009: 160 h / SEK 240,000, June target) → fewer hours, Principal-Engineer rate, July target. Scope remains software-only — consistent with the at-speed/BOM exclusions flagged in E-010; high-speed testing is deferred to Phase C, and platform/mechanics work to Phase B.

SNPS-provided Phase A funding SOW draft: "Statement of Work — MicroHAPS bootstrap" (June 4 2026 DRAFT; docs/b12n-ht3/Statement of Work E-sharp MicroHAPS bootstrap v1 DRAFT.docx; from Christine Ballesteros, last edited Mathias Svensson). This is the funding vehicle for Phase A (cf. E-015/E-020).

Parties: Synopsys Sweden AB (Lund) ↔ E-Sharp Software Solutions AB ("Vendor", Kävlinge). Governed by the Master Terms & Conditions dated 2024-11-05. Effective target 2026-06-05, for the SNPS HAPS R&D business unit.

Services:

1. Begin software development + integration with E-Sharp Accordion infrastructure, toward a longer-term goal (full solution not in this SOW; exact definition pending) of an E#-provided MicroHAPS (PCBA) based platform, fully supported & documented.
2. For DUT B12-N_PB (B12N HT3 panel board): test development (snowball test, TestStand + Synplex integration, potentially more tests), test specification, and rudimentary user instructions in the Synplex test — to support a factory test deployment using SNPS-provided fixture hardware.
3. In collaboration with Synopsys; plus project coordination & technical follow-up.

SNPS provides: Synopsys laptop (software + licenses); required HAPS hardware (microHAPS prototype platform, DUTs, test adapters, boards). Tools are SNPS Confidential, used-not-modified, returned/destroyed at end.

Assumptions (selected): requirements "described well, but parts … engineered or innovated during the project"; external ref "Production Test guidance for B12-N_PB"; joined development — SNPS provides key gating components: high-load FPGA designs + software/script/firmware to enable tests & logging (per PRD "Prerequisites"); if SNPS deliverables are late, this shall not gate payment; factory deployment & training are NOT in scope.

Ownership: results/deliverables are sole property of Synopsys (work-for-hire). Vendor may deliver its own/third-party proprietary or OSS products (listing on request); third-party IP is declared by Vendor and purchased by Synopsys.

Period: ~2026-06-05 through latest 2026-11-01 (or termination). Compensation milestone/deliverable based.

Commercials: hourly; monthly invoicing with timesheets. Cap 300,000 SEK (project target cost) + 50,000 SEK contingency (on SNPS written approval) = 350,000 SEK max; travel excluded (Vendor's cost; expected at start & end).

Status: DRAFT pending E# review/feedback (see review-points notice) and signature.

Decision: E# accepts the Phase A SOW ("MicroHAPS bootstrap", E-021) as-is and signs it without requesting the E-022 changes.

Rationale: terms are acceptable and E# prioritises starting Phase A quickly (July target). The SOW is favourable on the key points — SNPS-late deliverables do not gate payment, +50k SEK contingency available, factory deployment out of scope. The E-022 review points (payment-model wording, prototype-fixture checkbox, etc.) are accepted/waived.

Residual to manage under the signed terms: the ownership clause makes all results Synopsys property — E# should still declare its Accordion infrastructure (and any reused E# IP / OSS) as Vendor proprietary under the SOW clause that permits it (listing on request), so E# retains its own IP.

Effect: Phase A is funded and greenlit — B12-N_PB test development; cap 300k SEK (+50k contingency), period through 2026-11-01, July deploy target (MS-005). Supersedes the review/feedback actions (E-020, E-022 now closed).

All open commercial/proposal items on B12-N are now approved and agreed with Synopsys. The earlier warnings E-010 (scope delta), E-012 (proposal detail alignment), and E-014 (engagement-to-LCA) are resolved.

Decision: E# implements the Synopsys-provided SOW (Yiming's Production Test SOW for B12-N_PB) as the authoritative scope. The scope delta is resolved by adopting the SOW rather than the narrower E# quote — i.e. deliver to the SOW's test list / coverage matrix (REQ-PT-001…007), not the reduced quote scope.

Rationale: Synopsys (Vic) required proposal detail aligned to the SOW and continuity to LCA; agreeing to implement the SOW directly removes the misalignment and the scope-narrowing tension in one step. No commercial items remain open.

Implication for execution: work now proceeds against the SOW. The remaining gating items are technical/schedule, not commercial — MS-001 (HW received, 2026-06-16) still depends on Synopsys delivering Snowball units + the HT3→HT4 adapter, and the TC-PT/TC-TS testcases need implementation + verification records for MS-003.

Decisions

• Frame: Octave 40×40×20 extrusion
• Fixture plates: Keep Synopsys B12 and HT3 fixture plates and existing mechanics from those fixtures
• Micro-HAPS mounting: Use the same Synopsys plate for mounting the Micro-HAPS inside the fixture
• Custom parts: Anything not sourced from Synopsys — create custom
• Fixture plate material: Acrylic now, aluminium later
• Cable guides: Same type as in B12 CB
• Fixture contents: Must fit Micro-HAPS, A2, PC, and power for everything

Rationale

Concept/prototype phase — validate mechanical fit and layout before committing to aluminium parts.

Rejected alternatives

• Aluminium plate immediately: rejected to reduce cost and lead time during prototype validation phase.

E# has access to Empower (BOMs + 3D mechanical files). Dave asks E# to review the BOMs from the perspective of E# procuring them and give feedback / concerns / thoughts; discuss if anything should change or if alternative vendors should be added.

Part numbers:

• SH100008609 — microHAPS BASE KIT: Open Frame Chassis + Base Plate + Top Plate + microHAPS + ATX Power Supply.
• SH100009012 — HT4-HT3 EXT ADPTR FIXTURE KIT: Base Kit + fixturing for the HT4→HT3ext Adapter (both PCBA test and Enclosure Test).
• SH100009059 — B12-N PANEL BOARD FIXTURE KIT: Base Kit + fixturing for the B12-N Panel PCBA.

→ Pull these from Empower, review procurement feasibility/vendors, and reply to Dave with feedback.

The open-frame chassis appeared to get damaged in shipping to Lund. For the June deployment the current open-frame mechanics are used as-is; for post-June deployments, E# is invited to propose a different enclosure — to be discussed from both BOM-procurement and functionality/ergonomics perspectives.

Constraints / must-haves (DU):

• A fan grill is needed and must be incorporated into the design — ideally remove the fan altogether.
• Do NOT throw out / redo the mechanics that interface to the DUT PCBA — that interface must be preserved and adapted onto whatever enclosure is agreed.

→ E# action (post-June): propose an alternative enclosure meeting the above; discuss with Dave.

DU corrected two assumptions Daniel had made — capture so they are not repeated:

1. Power control IS critical (Daniel had assumed "not critical for project"). It matters for how a DUT is loaded and unloaded. microHAPS R1 tape-out is done; we need to understand what will be proposed on Rev0 for power control. → clarify Rev0 power-control behaviour before relying on it.

2. ALL programming and testing must be done through the microHAPS. The benchtop setup (Lund team, used for e.g. MPS-regulator programming) is interim ONLY, used until the microHAPS setup is ready. → do not design the production flow around the benchtop tester.

3. SSTDM HDL is available and enables at-speed testing; it will run on some assemblies (beyond the HCI/GPIO/I2C baseline).

The SOW references bare boards/parts by SH number, whereas the earlier Empower BOMs (E-002 action) reference fixture KITs. Keep both straight when procuring:

From the SOW (bare boards):

• B12-N_PB board (the DUT): SH100008620
• microHAPS (a.k.a. KU5p test board): SH100008193
• Generic HT3x2-HT4x2 adapter board: SH100008643
• Snowball

From the April email (Empower fixture kits):

• microHAPS BASE KIT: SH100008609 (Open Frame Chassis + Base Plate + Top Plate + microHAPS + ATX PSU)
• HT4-HT3 EXT ADPTR FIXTURE KIT: SH100009012
• B12-N PANEL BOARD FIXTURE KIT: SH100009059

→ The kits bundle the bare boards with chassis/fixturing. Reconcile these when reviewing the BOMs for E# procurement (links to action E-002).

Tracked-change comments in the SOW docx from Johan Aasa (2026-04-02), against the I2C/IDPROM section (§4.2):

1. IDPROM (0x50) is present only on Channel 1 — not on all five channels.
2. The IDPROM will only hold board-specific ID data.

→ Reflected in REQ-PT-002 acceptance. Confirm the production test addresses IDPROM only on Channel 1 and validates board-specific ID content.

From the SOW §7–§8:

• Assumptions & constraints (§7) are TBD — to be finalized with Hardware Engineering, Test Engineering, and the Manufacturing/Test Partner during the test readiness review. → schedule/track this review; the assumptions feed limit derivation and coverage scope.
• Change management (§8): any change to test scope, coverage, or requirements must go through a formal SOW amendment approved by all stakeholders. → out-of-scope items (system/board validation & characterization, repair procedures, firmware feature development beyond test enablement) require an amendment to bring in.

The E# quote (E-009) explicitly excludes several items the SOW (E-005) implied or required. These gaps should be reconciled with Synopsys before commitment, and any agreed change handled via the formal SOW-amendment / change process (both docs require it).

• At-speed verification — SOW §4.3 / REQ-PT-003 requires HT3/HT4 at-speed testing, but the quote lists "Configuration of tests to run via the microHAPS platform for at-speed verification" as OUT of scope. The quote covers functional test via Snowball/TestStand, not at-speed via microHAPS. → Clarify who delivers at-speed coverage and whether REQ-PT-003 is fully met by this engagement.
• BOM / Empower review — Dave asked E# to review the Empower fixture-kit BOMs (action E-002), but the quote lists "Review of BOMs, CAD models, or documentation made available via Empower" as OUT. → E-002 is likely not covered by this quote.
• Test hardware / fixturing — quote excludes "Design, manufacture, or modification of test hardware, fixturing, PCBs, or enclosures"; E# only assembles SNPS-provided HW. SOW §5 listed test fixtures + their BOM as deliverables. → Confirm fixturing is fully SNPS-supplied.
• HDL / FPGA / firmware — quote excludes development/modification (consistent with SNPS ownership). Note this means E-001's turn-key aspiration (E# owning firmware/RTL) is not part of this project's quote.
• Enclosure rework — quote excludes "Mechanical redesigns or enclosure rework", contradicting the post-June enclosure-proposal opportunity (E-003).
• Production deployment — quote excludes "Production ramp-up, volume manufacturing support, or factory deployment" and long-term maintenance, but MS-001 lists "assemble & validate N fixtures and ship to the factory" and the SOW targets CM/Ops release. → Clarify the boundary between this lab-station quote and production/factory deployment.

→ Action: align SOW expectations vs quoted scope with Dave Upton; record agreed scope via amendment.

The quote's effort (~160 h), cost (SEK 240,000), and June 2026 timeline are contingent on the following (confirm at the SOW test-readiness review, E-008):

• All test HW (microHAPS, Snowball controllers, fixturing, PSUs, accessories) is provided by Synopsys, delivered on schedule, and functional.
• Provided HDL / FPGA images / firmware are final — no modification by E#.
• The DUT & adapters are mechanically compatible with the provided fixture — no mech redesign / enclosure rework.
• E# gets timely access to Synopsys systems/environments, including Synplex.
• Synopsys provides timely input, feedback, and approvals.
• Changes to hardware readiness, test requirements, or external dependencies may impact schedule, effort, and cost.

Email from Vic Juneja (Synopsys), 2026-05-21, to Daniel Rhodin & Daniel Hansson, following the morning's discussions. This is SNPS's direct response to the scope gap flagged in E-010.

Vic's position: the SOW / technical-deliverables section of E#'s counter-proposal (E-009) needs to be more aligned with the detail captured and proposed by Yiming in the SOW (Production Test SOW for B12-N_PB.docx), and not "skimpy on technical detail" as in E#'s quote (B12N-HT3 Panel Test Station Quote and Proposal – May 2026.docx). Specifically, E# should provide a detailed list of tests & coverage.

(New context: the B12-N_PB SOW was authored by Yiming.)

→ Action: revise E#'s proposal technical deliverables to match the SOW's level of detail — i.e. a documented test list + Test Coverage Matrix (SOW §5) mapped to REQ-PT-001…007.

Mitigation proposed by Vic (SNPS), 2026-05-21, to address deliverable misalignment (E-012):

Because producing the detailed info (list of tests & coverage) is real work, for a few early engagements/SOWs Synopsys would consider paying E# for a few hours to produce a detailed Test Functional Spec — so there is less risk of misalignment on deliverables. The expectation is that after a few early engagements both teams converge on expectations, leaving little to interpretation.

→ Decision needed: agree this paid-spec mechanism for B12N-HT3 (and future early SOWs) — i.e. a small funded work package for E# to author the detailed test functional spec up front.

Scope/duration constraint from Vic (SNPS), 2026-05-21:

E# ownership/engagement must continue until the LCA build — including the CM factory environment replicated in E#'s lab (E# not necessarily on-site at the CM). Rationale: HW/DUT maturity — and therefore test maturity — is only reached at LCA. If the E# engagement closes earlier than LCA, another SOW cycle will be required.

Example cited: the B12 CB0/CB1 test engagement (unique in nature) — its deliverables are not yet at the desired test-coverage level; another test release with additional/updated tests is needed.

→ Implication for B12N-HT3: the engagement scope/duration should run to LCA, not stop at the lab-station bring-up in E#'s current quote (tension with the quote's "initial delivery" boundary — see E-010). Factor this into the revised proposal and commercials.

Action items agreed at the 2026-06-03 meeting (owners noted):

Synopsys:

• Provide Snowball units (blocking — see issue)
• Provide / confirm the HT3→HT4 adapter (blocking — see issue)
• Assign a technical contact person
• Mathias to provide an SOW proposal for Phase A
• Mathias to share the presentation shown during the meeting

E-Sharp:

• Prepare the Phase B platform proposal

Email from Mathias Svensson (Synopsys business owner, mathias@synopsys.com), 2026-06-04, replying to Daniel Hansson's meeting notes (2026-06-03).

• Alignment confirmed: Mathias is "in general aligned" with the meeting notes → this confirms decision E-015 (the Phase A/B/C structure and Phase A scope/commercials), which had been recorded as pending SNPS confirmation.
• Phase A SOW draft received: Mathias "attached an SOW draft … that could be used to cover and fund phase/project A" and asks for E# feedback as early as possible. This fulfils the E-019 action "Mathias to provide an SOW proposal for Phase A."

→ E# action (time-sensitive): review the Phase A SOW draft and return feedback ASAP. When reviewing, reconcile against: the scope-delta items still open (E-010), Vic's request for SOW-level technical detail / a test list + coverage matrix (E-012), and the LCA-ownership constraint (E-014). This SOW is the funding vehicle for Phase A (120 h, July delivery — E-015).

(Still outstanding from E-019: Mathias to share the meeting presentation. The SOW draft document itself is not yet filed here — capture its contents once shared.)

Feedback points for the Phase A SOW draft (E-021), to return to Mathias ASAP (the E-020 action):

• Commercials vs estimate: SOW caps at 300k (+50k contingency = 350k) vs the meeting-notes estimate ~270k (120 h, E-015) — gives buffer, but confirm the basis. Payment model is worded inconsistently: "hourly, invoiced monthly with timesheets" vs "compensation solely based on deliverables/milestones achieved" — clarify hourly-actuals vs milestone-based.
• External requirements ref: SOW cites "Production Test guidance for B12-N_PB" — confirm this is the intended/available document (cf. the Production Test SOW captured as E-005) and that it carries the test-list + coverage detail Vic requested (E-012).
• Favorable terms to confirm: factory deployment & training explicitly out of scope (consistent with E-010); SNPS-late-does-not-gate-payment — protective given the E-016 hardware blockers (Snowball/adapter); +50k contingency available.
• Open checkbox: "related order of prototype fixtures/material" — neither option is selected in the draft; clarify whether a separate fixture order is needed.
• Vendor IP: ensure E#'s Accordion infrastructure is declared as Vendor proprietary (the ownership clause makes results SNPS property) so E# retains its own IP.
• Platform scope: the longer-term MicroHAPS-platform goal is "exact definition pending" — Phase B territory (E-017); keep it out of the Phase A commitment.
• Period: runs to 2026-11-01 (outer bound) although Phase A targets July (E-015) — note the buffer vs the July milestone (MS-005).

This project depends on ETT00000008 R0, which now has a successor: ETT00000008 R1. Review whether to upgrade the dependency (please_project_link) or record why you are staying on R0 (please_entry_create kind=decision).

Received 3 Snowball units from Synopsys on 2026-06-08.

Serial numbers:

• x010753
• x010738
• x010746

These are one of the two hard blockers from [[E-016]] (Snowball units + HT3→HT4 adapter) gating the B12-N DUT test implementation (MS-003 onward) and contributing to MS-001 (Hardware received from Synopsys, target 2026-06-16). The HT3→HT4 adapter (SH100008643) is still outstanding — confirm before MS-001 can be closed.