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B12-N HT3 Panel Board Test

ETT00000009 · Rev R0

in_progresstestelectronicsAvstämning

Production test solution for the B12-N HT3 Panel Board (B12-N_PB, SH100008620; Synopsys DUT), built on the microHAPS platform (depends on ETT00000008).

  • DUT: B12-N HT3 Panel Board — HT3-to-HT4 panel board, 5 independent channels
  • Tester: microHAPS (SH100008193) + HT3x2-HT4x2 adapter (SH100008643) + Snowball
  • Engagement phased A/B/C (Mathias Svensson, 2026-06-03): Phase A = software dev & integration (Snowball/TestStand/Synplex), delivered within July 2026. Phase B = multi-DUT interchangeable-panel platform (separate SOW). Phase C = alternative high-speed test solution.
  • Primary domain: test; secondary: electronics
  • Repo: https://github.com/esharpab/testdevelopment-snps-microhaps

Depends on the microHAPS platform project (ETT00000008 R0, id 43).

Everything here lives inside a Project (a code + revision, e.g. ESH10000540 R3). The backbone is the V-model, read top-to-bottom: define what the product must do, plan how to prove it, execute the proof on real units, then learn from the field — and the Loop closes back up to the top.
This map is live: a block is green with a count when this project actually has that entity, and dashed/dim when it’s empty. Click any block to open its tab; hover for details. Arrows are the meaningful links; the implicit “belongs to this Project” edge is left out for legibility.

What each thing means

Requirement
One thing the product must do or satisfy — the “what”.
Test Case
A defined check that proves one or more requirements — the “how we prove it”. A verified_by trace link ties a test case to the requirement(s) it covers; that link is exactly what Coverage % counts. (So: a test case refers to the requirements it verifies.)
Verification Plan
A named grouping of test cases, approved before a test campaign and optionally gated by a milestone.
Verification Record
The result of running one test case against one unit: pass / fail / error / na. This is the evidence a requirement is actually met.
DUT
Device Under Test — an individual physical unit (by serial number) that records and test data attach to.
Deviation
A documented waiver against a verification record (e.g. accept a known non-conformance, with justification).
Entry
A knowledge note: a decision (settled choice), notice (assumption / risk / open question), issue (tracked problem), or concept (idea under exploration). It can attach to any other entity.
Design Rule
A reusable, checkable engineering constraint. Running the checks turns each violation into a Conflict.
Conflict
An open flag raised by a failed design-rule check (or an end-of-life / component-library issue) that needs resolving.
Milestone
A dated gate; verification plans can be tied to it.
Field Issue (RMA)
A failure reported from the field on a returned unit; Root-Cause Analysis explains why it happened.
The Loop (S-16)
loop_trace reconciles a field issue against that unit’s own verification record (did it pass at the edge of the band?). closes_loop records the corrective decision or design rule so the lesson is captured — and clears the project’s open-loop count.
Interface / Port
A contract between projects; each port can be driven by a requirement (and cascade one into the connected project).
BOM Component
A part on this project’s bill of materials, optionally linked to the shared Component Library.
GRR Study
A Gauge R&R study measuring how repeatable a test case’s measurement is.
Test Data
Production / Maestro run results recorded against DUTs — the population behind a single verification record.
0% Coverage
0% Done
0 Requirements
13 Test Cases
1 Blockers
24 Open Entries

Timeline

Color = derived gate state · hover a tile for its note.
overdue / blocked
Hardware received from Synopsys
Jun 16, 2026· 0/1
achieved
Concept Fixture Gate
Jun 18, 2026· 3/3
overdue / blocked
µHAPS platform first start (smoke test)
Jun 26, 2026· 0/1
overdue / blocked
Tests implemented & verified
Jul 15, 2026· 0/1
overdue / blocked
TestStand sequence + user instructions
Jul 24, 2026· 0/1
approaching
Deployed to Synplex
Jul 31, 2026· 0/1
not started
Shipped to factory & validated at manufacturing
Aug 10, 2026· 0/1
not started
Final release
Aug 17, 2026· 0/1
not started
🏁 Release
· 2/6

Status & gates

Chronological — Release is the final gate. Derived & read-only; edit via trace_milestone_* tools.
MS-001Hardware received from Synopsys overdue / blocked 0/1 metdue 2026-06-16
pending Blocked by E-016: Phase A blocked until prerequisites met: Snowball units + HT3→HT4 adapter + SNPS technical contact
  • E-016 still open
MS-008Concept Fixture Gate achieved 3/3 metdue 2026-06-18
met Blocked by E-028: 3D model not yet complete
met Blocked by E-029: 3D PDF not yet exported and shared
met Blocked by E-030: Acrylic plate not yet cut
MS-002µHAPS platform first start (smoke test) overdue / blocked 0/1 metdue 2026-06-26
pending After MS-001: Hardware received from Synopsys
  • MS-001 not yet achieved
MS-003Tests implemented & verified overdue / blocked 0/1 metdue 2026-07-15
pending After MS-002: µHAPS platform first start (smoke test)
  • MS-002 not yet achieved
MS-004TestStand sequence + user instructions overdue / blocked 0/1 metdue 2026-07-24
pending After MS-003: Tests implemented & verified
  • MS-003 not yet achieved
MS-005Deployed to Synplex approaching 0/1 metdue 2026-07-31
pending After MS-004: TestStand sequence + user instructions
  • MS-004 not yet achieved
MS-006Shipped to factory & validated at manufacturing not started 0/1 metdue 2026-08-10
pending After MS-005: Deployed to Synplex
  • MS-005 not yet achieved
MS-007Final release not started 0/1 metdue 2026-08-17
pending After MS-006: Shipped to factory & validated at manufacturing
  • MS-006 not yet achieved
Release / Readiness not started 2/6 met
pending Requirements approved
  • REQ-PT-003: draft
  • REQ-PT-005: draft
  • REQ-PT-007: draft
  • REQ-PT-004: draft
  • REQ-PT-006: draft
  • REQ-TS-004: draft
  • REQ-TS-005: draft
  • REQ-TS-001: draft
  • REQ-TS-002: draft
  • REQ-TS-003: draft
pending Coverage ≥ 100%
  • No requirements in scope
pending All test cases pass
  • 0/13 passed
  • 13 not yet run
pending No blocking issues open
  • E-016: open blocker
met Deviations resolved
met Interfaces frozen
Composition 1 dependency need attention: ETT00000008 R0 (amber, newer revision available)

Test Cases

0 Pass 0 Fail / Deviated 0 N/A 13 Open0 / 13 Maestro impl.

Coverage — 0.0% · Done — 0.0%

13 of 13
CodeTitleCategoryCoverageStatus
REQ-PT-001 Power integrity & protection power
REQ-PT-002 I2C communication & device identification (IDPROM) comms
REQ-PT-003 HT3/HT4 interface & at-speed connectivity interface
REQ-PT-004 Voltage negotiation (Vn_CONx) power
REQ-PT-005 Telemetry & thermal metrology
REQ-PT-006 Power module (PSM / MPM54304) configuration power
REQ-PT-007 Automated test integration & release (TestStand/Synplex) automation
REQ-TS-001 Requirement Coverage coverage
REQ-TS-002 Measurement Uncertainty metrology
REQ-TS-003 Calibration Interval metrology
REQ-TS-004 Pass/Fail Criteria quality
REQ-TS-005 Repeatability (GR&R) metrology
REQ-TS-006 Test Limit Derivation Documented quality