Micro-HAPS
ETT00000008 · Rev R1
in_progresstestelectronics
Micro-HAPS R1 — successor of R0 (project id 43, ETT00000008 R0). Synopsys at-speed (high-speed I/O) test board based on a Xilinx Kintex UltraScale+ KU5P FPGA; E-Sharp test development work.
- Primary domain: test (at-speed test development); secondary electronics (KU5P FPGA board).
- Vendor: Synopsys (SNPS); HW designer Martin Wang.
- R1 PCB/PCBA: TBD (revision of SH100008192/SH100008193 "KU5P_Generic_Tester"). Host control via FTDI FT4232H service port.
- ⚠ Design docs (schematic/BOM/spec) are SYNOPSYS CONFIDENTIAL; customer BOM not imported into the Trace component library.
- Repository: https://github.com/esharpab/testdevelopment-snps-microhaps
Purpose of this project: re-run the R0 analyses on R1 (starting with the JTAG / FTDI service-port signal chain) and diff against R0 to see what was fixed vs. carried over. Key R0 findings to verify on R1: open-drain TDO buffer U9 (SN74AUP1G07 + R139 10K) speed limiter [R0 E-038]; C10–C13 10nF JTAG line-cap NM-vs-ODB discrepancy [R0 E-039].
Everything here lives inside a Project (a code + revision, e.g. ESH10000540 R3).
The backbone is the V-model, read top-to-bottom: define what the product must do, plan how to prove it,
execute the proof on real units, then learn from the field — and the Loop closes back up to the top.
This map is live: a block is green with a count when this project actually has that entity,
and dashed/dim when it’s empty. Click any block to open its tab; hover for details.
Arrows are the meaningful links; the implicit “belongs to this Project” edge is left out for legibility.
What each thing means
- Requirement
- One thing the product must do or satisfy — the “what”.
- Test Case
- A defined check that proves one or more requirements — the “how we prove it”. A verified_by trace link ties a test case to the requirement(s) it covers; that link is exactly what Coverage % counts. (So: a test case refers to the requirements it verifies.)
- Verification Plan
- A named grouping of test cases, approved before a test campaign and optionally gated by a milestone.
- Verification Record
- The result of running one test case against one unit: pass / fail / error / na. This is the evidence a requirement is actually met.
- DUT
- Device Under Test — an individual physical unit (by serial number) that records and test data attach to.
- Deviation
- A documented waiver against a verification record (e.g. accept a known non-conformance, with justification).
- Entry
- A knowledge note: a decision (settled choice), notice (assumption / risk / open question), issue (tracked problem), or concept (idea under exploration). It can attach to any other entity.
- Design Rule
- A reusable, checkable engineering constraint. Running the checks turns each violation into a Conflict.
- Conflict
- An open flag raised by a failed design-rule check (or an end-of-life / component-library issue) that needs resolving.
- Milestone
- A dated gate; verification plans can be tied to it.
- Field Issue (RMA)
- A failure reported from the field on a returned unit; Root-Cause Analysis explains why it happened.
- The Loop (S-16)
loop_tracereconciles a field issue against that unit’s own verification record (did it pass at the edge of the band?).closes_looprecords the corrective decision or design rule so the lesson is captured — and clears the project’s open-loop count.- Interface / Port
- A contract between projects; each port can be driven by a requirement (and cascade one into the connected project).
- BOM Component
- A part on this project’s bill of materials, optionally linked to the shared Component Library.
- GRR Study
- A Gauge R&R study measuring how repeatable a test case’s measurement is.
- Test Data
- Production / Maestro run results recorded against DUTs — the population behind a single verification record.
0%
Coverage
0%
Done
0
Requirements
1
Blockers
21
Open Entries
Timeline
Color = derived gate state · hover a tile for its note.not started
🏁 Release
Status & gates
Chronological — Release is the final gate. Derived & read-only; edit viatrace_milestone_* tools.Release / Readiness not started 2/6 met
pending Requirements approved
- No requirements in scope
pending Coverage ≥ 100%
- No requirements in scope
pending All test cases pass
- No test cases in scope
pending No blocking issues open
- E-002: open blocker
met
Deviations resolved
met
Interfaces frozen
Coverage — 0.0% · Done — 0.0%
| Code | Kind | Title | Severity | Scope | Status | Milestone | Created |
|---|---|---|---|---|---|---|---|
E-001 |
concept | R1 JTAG analysis & R0↔R1 diff — TDO open-drain root cause NOT fixed in R1 (affects FTDI and XJTAG); voltage chain is consistent | warning | next_revision | open | — | 2026-06-06 |
E-002 |
issue | [R2] Replace open-drain TDO buffer U9 — JTAG TDO return path caps at ~1 MHz (open-drain SN74AUP1G07 @1.8V + R139 10K→3.3V) | blocking | next_revision | open | — | 2026-06-06 |
E-003 |
notice | I2C subsystem walkthrough — R1 (four checks + R0→R1 diff / fix verification) | info | record | open | — | 2026-06-07 |
E-004 |
issue | R1 I2C: Si5340 (1.8V I2C?) moved onto the 3.3V FPGA_I2C segment with no level translation — possible relocated E-045 | warning | record | open | — | 2026-06-07 |
E-005 |
issue | VERIFY ON R1: two TCA9803 static-offset buffers (U60 FTDI + U5 FPGA bridge) both fitted on the management bus — confirm they don't share a segment without enable orchestration (latch / V_OL-stack risk) | warning | action | open | — | 2026-06-11 |
E-006 |
notice | R1 swapped U50/U54 (the MGB I2C level translators) from PCA9306 to TCA9803, but their TCA9803 VCCA (A-side supply, pin 1) and EN (pin 5) re… | info | record | open | — | 2026-06-14 |
E-007 |
notice | [CON-001] Design-log corroboration (R0.0→R1.0 log, tab 'R0.0 --> R1.0', severity-3 entry): the U50/U54 PCA9306→TCA9803 swap was a deliberat… | info | record | open | — | 2026-06-14 |
E-008 |
notice | [observation:6] Design-log context (R0.0→R1.0, severity-2 entry) for the FPGA_I2C nets flagged as 'pull-up missing': quote — "There was no … | info | record | open | — | 2026-06-14 |
E-009 |
notice | Design-log R0.0→R1.0 digest (substantive entries from SH100008193_R1.0_KU5P_Generic_Tester_DesignLog.xlsx, tab 'R0.0 --> R1.0'): (1) sev3 —… | info | record | open | — | 2026-06-14 |
E-010 |
notice | [observation:7] Trace cross-check: OBS-7 independently rediscovers the existing BLOCKING R2 item E-002 ("Replace open-drain TDO buffer U9")… | info | record | open | — | 2026-06-14 |
E-011 |
notice | [CON-001] Trace cross-check: CON-001 EXTENDS the prior R1 I2C walkthrough E-003, which recorded the MGB translator swap as "PCA9306 → TCA98… | info | record | open | — | 2026-06-14 |
E-012 |
notice | [observation:7] CORRECTION — OBS-7 refuted. JTAG TDO must be driven push-pull (point-to-point, single driver); an open-drain buffer cannot … | info | record | open | — | 2026-06-14 |
E-013 |
notice | [E-004] Enrichment result (Si5340A datasheet, cached — answers E-004's open question). The Si5340 serial-interface I/O voltage (SDA pin13 /… | info | record | open | — | 2026-06-14 |
E-014 |
notice | PU10 (P1V8_MGTVCCAUX LDO) feedback node P1V8_MGTAVCCAUX_FB — a high-impedance ~0.8 V reference node — is routed off the regulator on sheet … | info | record | open | — | 2026-06-20 |
E-015 |
notice | All four HT3 DUT-interface I2C channels (HT3_0..3) place an RC low-pass on the PCA9547 mux's DOWNSTREAM open-drain channel pins: a series 3… | info | record | open | — | 2026-06-20 |
E-016 |
notice | U47 (PCA9547BS) uses an I2C-PROGRAMMED 8-channel I2C mux to fan the host bus (MUX_I2C, mastered by FPGA U1 and shared with the MCP3424 ADC … | info | record | open | — | 2026-06-20 |
E-017 |
notice | P1V8_MGTVCCAUX is always-on: PU10 (TPS7A8101 LDO) is sourced from P3V3_G (3.3V STANDBY at PJ1), so the FPGA's GT transceiver-auxiliary supp… | info | record | open | — | 2026-06-21 |
E-018 |
notice | JTAG is DISABLED by default and the external XJTAG port is not independent. JTAG_FTDI_EN_N idles HIGH (R133 10k→P3V3_STBY; the GND pull-dow… | info | record | open | — | 2026-06-21 |
E-019 |
notice | D2 (BAV99 dual-diode rail clamp) is tapped on the CONNECTOR side of the series resistor, so instead of protecting the fan PWM line it becom… | info | record | open | — | 2026-06-22 |
E-020 |
notice | The fan header's +12V (J21.2) connects directly to the main board P12V rail with no fan-dedicated current limit / eFuse / fuse. P12V is the… | info | record | open | — | 2026-06-22 |
E-021 |
notice | U4 (M24C02-FMC6TG fitted in layout / AT24MAC402 in BOM — identity UNRESOLVED), the central-bus ID-EEPROM at 0x50 (on I2C_SDA0/SCL0, P3V3_ST… | info | record | open | — | 2026-06-22 |
E-022 |
notice | U54 and U50 (TCA9803DGKT active I2C bus buffers) have their A-side supply VCCA (pin 1) fed ONLY through a 200k resistor from P3V3_VCCO, whi… | info | record | open | — | 2026-06-22 |