E-007 — Functional Block Diagram — Accordion Test Adapter R1 concept

Hypothesis

Top-level functional decomposition of the Accordion Test Adapter R1, agreed during concept session 2026-06-08.

Bus topology (2026-06-09):

• UART · SPI: series daisy-chain through all module slots
• I2C: unique per slot — pin-strap selects which slot to address (1-of-4)

graph LR
    USBPD["USB PD
20V"]
    FTDI["FTDI USB-Serial
Vertical USB · REQ-003"]

    subgraph A2_LINK["Accordion A2 link"]
        CTOP["Com-Top
input connector"]
    end

    subgraph PWR["Power Management"]
        PM["20V distribution
5V / 3V3 / 1V8 generation
2.5V VREF = module 2.5V rail
Per-slot switches ≥1A
Shunt meas. 0–1A · Power LEDs"]
    end

    I2C_SW["I2C Slot Select
Pin-strap · DEC-002
1-of-4"]

    NTOP["N-Top"]
    SODIMM["SO-DIMM"]
    M2["M.2"]
    CTOP_OUT["Com-Top
reg + mini"]

    USBPD -->|"20V"| PM
    CTOP -->|"20V"| PM
    CTOP -->|"I2C"| I2C_SW
    I2C_SW -.->|"selects 1 slot"| NTOP & SODIMM & M2 & CTOP_OUT
    CTOP -->|"UART · SPI"| NTOP -->|"UART · SPI"| SODIMM -->|"UART · SPI"| M2 -->|"UART · SPI"| CTOP_OUT
    PM -->|"20V · 5V · 3V3 · 2.5V · 1V8"| NTOP & SODIMM & M2 & CTOP_OUT
    FTDI --> NTOP & SODIMM & M2 & CTOP_OUT

Key decisions reflected

• DEC-001: 20V from USB PD
• DEC-002: I2C slot select via pin-strap (1-of-4; I2C originates from A2 via Com-Top)
• DEC-003: Local 5V, 3V3, 1V8 generation
• DEC-004: All rails (20V, 5V, 3V3, 2.5V, 1V8) to every module slot, max 1A per slot
• DEC-005: 2.5V VREF (REQ-001) serves as the module slot 2.5V rail

Open questions

None — all FBD-level questions resolved.

Next step

DS.01 schematic capture.