Accordion Test Adapter
ESH10000518 · Rev R1
Project visibility
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Everything here lives inside a Project (a code + revision, e.g. ESH10000540 R3).
The backbone is the V-model, read top-to-bottom: define what the product must do, plan how to prove it,
execute the proof on real units, then learn from the field — and the Loop closes back up to the top.
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and dashed/dim when it’s empty. Click any block to open its tab; hover for details.
Arrows are the meaningful links; the implicit “belongs to this Project” edge is left out for legibility.
What each thing means
- Requirement
- One thing the product must do or satisfy — the “what”.
- Test Case
- A defined check that proves one or more requirements — the “how we prove it”. A verified_by trace link ties a test case to the requirement(s) it covers; that link is exactly what Coverage % counts. (So: a test case refers to the requirements it verifies.)
- Verification Plan
- A named grouping of test cases, approved before a test campaign and optionally gated by a milestone.
- Verification Record
- The result of running one test case against one unit: pass / fail / error / na. This is the evidence a requirement is actually met.
- DUT
- Device Under Test — an individual physical unit (by serial number) that records and test data attach to.
- Deviation
- A documented waiver against a verification record (e.g. accept a known non-conformance, with justification).
- Entry
- A knowledge note: a decision (settled choice), notice (assumption / risk / open question), issue (tracked problem), or concept (idea under exploration). It can attach to any other entity.
- Design Rule
- A reusable, checkable engineering constraint. Running the checks turns each violation into a Conflict.
- Conflict
- An open flag raised by a failed design-rule check (or an end-of-life / component-library issue) that needs resolving.
- Milestone
- A dated gate; verification plans can be tied to it.
- Interface / Port
- A contract between projects; each port can be driven by a requirement (and cascade one into the connected project).
- GRR Study
- A Gauge R&R study measuring how repeatable a test case’s measurement is.
- Test Data
- Production / Assert run results recorded against DUTs — the population behind a single verification record.
Plan & time
Allocation grid →Nobody is allocated to this project in the next 8 weeks.
Nothing written for this week yet.
Nobody has written a narrative for this project yet.Timeline
Color = derived gate state · hover a tile for its note.Status & gates
Chronological — Release is the final gate. Derived & read-only; edit viatrace_milestone_* tools.Release / Readiness overdue / blocked 5/6 met1 failing
met Coverage ≥ 100%
- 21/21 requirements covered (100%)
failing All test cases pass
- 19/21 passed
- 2 failing: V-10, V-20
Test Cases
Coverage — 100.0% · Done — 90.5%
| Code | Kind | Title | Severity | Scope | Status | Milestone | Created |
|---|---|---|---|---|---|---|---|
C-001 |
notice | REQ-005 has no test case — add one to verify it? | info | action | withdrawn | — | 2026-06-26 |
E-001 |
decision | DEC-001 — 20V power input via USB PD (not Accordion A2 PSU) | info | record | open | — | 2026-06-08 |
E-002 |
decision | DEC-002 — I2C bus routing via manual pin-strap (not programmable switch) | info | record | open | — | 2026-06-08 |
E-003 |
decision | DEC-003 — Local rail voltage generation: 5V, 3V3, 1V8 from 20V input | info | record | open | — | 2026-06-08 |
E-004 |
decision | DEC-004 — Module slot power rails and current limit | info | record | open | — | 2026-06-08 |
E-005 |
decision | DEC-005 — 2.5V module slot rail is the VREF (REQ-001), same signal | info | record | open | — | 2026-06-08 |
E-006 |
notice | VREF IC must source sufficient current for all module slots on 2.5V rail | warning | action | open | — | 2026-06-08 |
E-007 |
concept | Functional Block Diagram — Accordion Test Adapter R1 | info | record | open | — | 2026-06-08 |