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Sparrow Test Adapter PCBA

ESH10000654 · Rev R0

in_progresselectronics
Reports Audit Log

Everything here lives inside a Project (a code + revision, e.g. ESH10000540 R3). The backbone is the V-model, read top-to-bottom: define what the product must do, plan how to prove it, execute the proof on real units, then learn from the field — and the Loop closes back up to the top.
This map is live: a block is green with a count when this project actually has that entity, and dashed/dim when it’s empty. Click any block to open its tab; hover for details. Arrows are the meaningful links; the implicit “belongs to this Project” edge is left out for legibility.

What each thing means

Requirement
One thing the product must do or satisfy — the “what”.
Test Case
A defined check that proves one or more requirements — the “how we prove it”. A verified_by trace link ties a test case to the requirement(s) it covers; that link is exactly what Coverage % counts. (So: a test case refers to the requirements it verifies.)
Verification Plan
A named grouping of test cases, approved before a test campaign and optionally gated by a milestone.
Verification Record
The result of running one test case against one unit: pass / fail / error / na. This is the evidence a requirement is actually met.
DUT
Device Under Test — an individual physical unit (by serial number) that records and test data attach to.
Deviation
A documented waiver against a verification record (e.g. accept a known non-conformance, with justification).
Entry
A knowledge note: a decision (settled choice), notice (assumption / risk / open question), issue (tracked problem), or concept (idea under exploration). It can attach to any other entity.
Design Rule
A reusable, checkable engineering constraint. Running the checks turns each violation into a Conflict.
Conflict
An open flag raised by a failed design-rule check (or an end-of-life / component-library issue) that needs resolving.
Milestone
A dated gate; verification plans can be tied to it.
Field Issue (RMA)
A failure reported from the field on a returned unit; Root-Cause Analysis explains why it happened.
The Loop (S-16)
loop_trace reconciles a field issue against that unit’s own verification record (did it pass at the edge of the band?). closes_loop records the corrective decision or design rule so the lesson is captured — and clears the project’s open-loop count.
Interface / Port
A contract between projects; each port can be driven by a requirement (and cascade one into the connected project).
BOM Component
A part on this project’s bill of materials, optionally linked to the shared Component Library.
GRR Study
A Gauge R&R study measuring how repeatable a test case’s measurement is.
Test Data
Production / Maestro run results recorded against DUTs — the population behind a single verification record.
0% Coverage
0% Done
0 Requirements
6 Test Cases
12 Open Entries

Timeline

Color = derived gate state · hover a tile for its note.
not started
🏁 Release
· 3/6

Status & gates

Chronological — Release is the final gate. Derived & read-only; edit via trace_milestone_* tools.
Release / Readiness not started 3/6 met
pending Requirements approved
  • REQ-TS-001: draft
  • REQ-TS-002: draft
  • REQ-TS-003: draft
  • REQ-TS-004: draft
  • REQ-TS-005: draft
  • REQ-TS-006: draft
pending Coverage ≥ 100%
  • No requirements in scope
pending All test cases pass
  • 0/6 passed
  • 6 not yet run
met No blocking issues open
met Deviations resolved
met Interfaces frozen
Attention 9 open entries

Test Cases

0 Pass 0 Fail / Deviated 0 N/A 6 Open0 / 6 Maestro impl.

Coverage — 0.0% · Done — 0.0%

0 Done 0 Partial 0 Not Started 0 Missing6 Draft0 Obsolete
Entries
17 of 17
CodeKindTitleSeverityScopeStatusMilestoneCreated
E-001 notice TA patch (P0) #1 — Rail A wired-OR fabric (FE_MPIO_8/10 + RELAY1/3, 10K to 2.5V) info record open — 2026-05-26
E-002 notice TA patch (P0) #2 — Rail B wired-OR fabric (FE_MPIO_9/11 + RELAY2/4, 10K to 2.5V) info record open — 2026-05-26
E-003 notice TA patch (P0) #3 — R48 mounted (was missing on as-assembled R0) warning record open — 2026-05-26
E-004 notice Next-rev TA — replace 2-rail ganged relay readback with 4-channel per-relay readback info record open — 2026-05-26
E-005 notice Q-TA-01 info record open — 2026-05-26
E-006 notice TA R0 schematic mfg P/N wrong on EGP10001847 — fix in next revision warning next_revision open — 2026-05-27
E-007 notice J5 VREF measurement via TA adds ~10 mV positive bias — root cause TBD warning action closed — 2026-05-27
E-008 decision TA R1: dedicated DMM_GND return required on Phoenix terminal block warning next_revision open — 2026-05-27
E-009 decision TA R1: provide 2.5 V + GND output connector for DSUB-9 audio loopback plug warning next_revision open — 2026-05-27
E-010 decision TA R1: add dedicated DMM_GND return between FE AGND and Phoenix P4 warning next_revision closed — 2026-05-27
E-011 notice DUT P0 rework: hand-wired FE J5-GND + TA-GND to Phoenix header for Host Accordion GND-bridge relay — add proper header in next TA revision info next_revision open — 2026-06-04
E-012 issue J4 polarity relays (ANALOG_POS Y0 / ANALOG_NEG Y1) do not flip the bus — both addresses yield identical DMM polarity warning action closed — 2026-06-18
E-013 issue TA AIN_P / AIN_N bus shorting appears incomplete — 8 ADC channels diverge when reading the same bus warning action withdrawn — 2026-06-18
E-014 issue N-Top ADC reads single-ended of one bus rail — values cluster at V/2; J4 differential-drive test approach is fundamentally wrong blocking action closed — 2026-06-18
E-015 decision TA address-mux powered at 5V; MPIO drive must be 5V (not 3.3V); Y0/Y1 → ANALOG_POS/ANALOG_NEG mapping was inverted info record open — 2026-06-18
E-016 notice P0 patch: galvanic GND wire from TA GND to PSU connector GND warning action open — 2026-06-18
E-017 issue TA next revision: AIN_P / AIN_N wired to wrong J4 pins (sign-inversion on the ADC differential) warning next_revision open — 2026-06-18