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Accordion M1

ESH10000597 · Rev R1

in_progresselectronicsAvstämning

Accordion M1 main board — R1. Successor to R0 prototype (id=13). USB-C PD 20V input, TPS259474 E-Fuse protection, regulated outputs 5V/12V/3.3V/2.5V/1.8V/2.5VREF. Module connectors: SO-DIMM (J9), M2 (J15), N-Top (J10/J11/J12), Comtop (J3). I2C bus mux, ADC monitoring, fan control, LED driver, RTC. Hammond enclosure.

Reports Milestones (5)Audit Log

Everything here lives inside a Project (a code + revision, e.g. ESH10000540 R3). The backbone is the V-model, read top-to-bottom: define what the product must do, plan how to prove it, execute the proof on real units, then learn from the field — and the Loop closes back up to the top.
This map is live: a block is green with a count when this project actually has that entity, and dashed/dim when it’s empty. Click any block to open its tab; hover for details. Arrows are the meaningful links; the implicit “belongs to this Project” edge is left out for legibility.

What each thing means

Requirement
One thing the product must do or satisfy — the “what”.
Test Case
A defined check that proves one or more requirements — the “how we prove it”. A verified_by trace link ties a test case to the requirement(s) it covers; that link is exactly what Coverage % counts. (So: a test case refers to the requirements it verifies.)
Verification Plan
A named grouping of test cases, approved before a test campaign and optionally gated by a milestone.
Verification Record
The result of running one test case against one unit: pass / fail / error / na. This is the evidence a requirement is actually met.
DUT
Device Under Test — an individual physical unit (by serial number) that records and test data attach to.
Deviation
A documented waiver against a verification record (e.g. accept a known non-conformance, with justification).
Entry
A knowledge note: a decision (settled choice), notice (assumption / risk / open question), issue (tracked problem), or concept (idea under exploration). It can attach to any other entity.
Design Rule
A reusable, checkable engineering constraint. Running the checks turns each violation into a Conflict.
Conflict
An open flag raised by a failed design-rule check (or an end-of-life / component-library issue) that needs resolving.
Milestone
A dated gate; verification plans can be tied to it.
Field Issue (RMA)
A failure reported from the field on a returned unit; Root-Cause Analysis explains why it happened.
The Loop (S-16)
loop_trace reconciles a field issue against that unit’s own verification record (did it pass at the edge of the band?). closes_loop records the corrective decision or design rule so the lesson is captured — and clears the project’s open-loop count.
Interface / Port
A contract between projects; each port can be driven by a requirement (and cascade one into the connected project).
BOM Component
A part on this project’s bill of materials, optionally linked to the shared Component Library.
GRR Study
A Gauge R&R study measuring how repeatable a test case’s measurement is.
Test Data
Production / Maestro run results recorded against DUTs — the population behind a single verification record.
98% Coverage
0% Done
46 Requirements
47 Test Cases
22 Open Entries

Timeline

Color = derived gate state · hover a tile for its note.
achieved
Tape-out
Jun 15, 2026
marker
Bring-Up
Jun 29, 2026
marker
Phase 1 Verification
Jul 3, 2026
marker
Phase 2 Verification
Jul 10, 2026
marker
Batch 1 Order
Jul 17, 2026
not started
🏁 Release
· 3/6

Status & gates

Chronological — Release is the final gate. Derived & read-only; edit via trace_milestone_* tools.
MS-001Tape-out achieveddue 2026-06-15
MS-002Bring-Up markerdue 2026-06-29
MS-003Phase 1 Verification markerdue 2026-07-03
MS-004Phase 2 Verification markerdue 2026-07-10
MS-005Batch 1 Order markerdue 2026-07-17
Release / Readiness not started 3/6 met
pending Requirements approved
  • REQ-040: draft
  • REQ-041: draft
pending Coverage ≥ 100%
  • 45/46 requirements covered (97.8%)
pending All test cases pass
  • 0/47 passed
  • 47 not yet run
met No blocking issues open
met Deviations resolved
met Interfaces frozen
Attention 7 open entries

Test Cases

0 Pass 0 Fail / Deviated 0 N/A 47 Open0 / 47 Maestro impl.

Coverage — 97.8% · Done — 0.0%

0 Done 0 Partial 45 Not Started 1 Missing2 Draft0 Obsolete
Entries
58 of 58
CodeKindTitleSeverityScopeStatusMilestoneCreated
C-001 notice REQ-014 has no test case — add one to verify it? info action open — 2026-06-10
E-001 notice [TBD] PoE input strategy decision needed warning record closed — 2026-06-02
E-002 notice [TBD] Push button / power-on MCU decision needed warning record closed — 2026-06-02
E-003 notice [TBD] MCU signals to module slots — routing decision needed warning record closed — 2026-06-02
E-005 notice [TBD] 12V rail inclusion decision needed warning record closed — 2026-06-02
E-006 notice REQ-011 implementation: Q8 removed, 5V routed via R147 info record closed — 2026-06-02
E-007 notice REQ-004 implementation: current limit set via R39 = 680Ω info record closed — 2026-06-02
E-008 notice REQ-005 implementation: dVdT ramp component values info record closed — 2026-06-02
E-009 notice M3×16mm N-Top screws cause collisions — length needs evaluation warning action open — 2026-06-02
E-010 decision PoE input strategy: active PoE 802.3at (45W) retained for R1 info record closed — 2026-06-09
E-011 decision PoE PD controller selected: TPS2373-4RGWR (TI, EGP10001943) info record closed — 2026-06-09
E-012 decision Push button / power-on MCU rejected for R1 info record open — 2026-06-09
E-013 notice 7805 footprint / part inconsistency suspected — verify before layout sign-off info record closed — 2026-06-09
E-014 decision 12V rail removed from Accordion M1 R1 — AMENDED by E-025 (rail repurposed to 20V VIN) info record open — 2026-06-09
E-015 decision 7805 retained in R1 — always-on 5V supply for 74HCS74 power latch info record open — 2026-06-10
E-016 decision 5V to RPi: fuse ∥ R147 (two mounting variants) info record open — 2026-06-10
E-017 notice M1 connector has 12 functional pin assignment errors — scope wider than DL-017 info record closed — 2026-06-10
E-018 notice M1 RPi connector pinout changes — full review required before tape-out info record closed — 2026-06-10
E-019 concept M1 connector — full R1 pinout (44-pin RPi header) info record open — 2026-06-10
E-020 notice R53 NM for R1 — latch held by R54→VCC; SHDN_N is from PI4IOE (U1), not RPi GPIO13 info record closed — 2026-06-10
E-021 decision decision: Bulk cap replacement: 1× Samsung CL32Y106KCV6PNE per position on VBUS and VPOE info record open — 2026-06-11
E-022 concept Future tech study: ESP32 as power-on / telemetry engine info next_revision open — 2026-06-11
E-023 notice DL-012 RPi header fit — evaluate mechanical retention vs. connector reselection info action open — 2026-06-11
E-024 notice Bus routing topology — SPI0 / SPI1 / UART / JTAG to module connectors info record closed — 2026-06-11
E-025 decision 12V rail repurposed to carry 20V (VIN) — amends E-014 info action open — 2026-06-11
E-026 notice RPI_ON net must have a test point in schematic info record closed — 2026-06-11
E-027 decision LM76005 CIN: 1× EGP10001944 (10µF/100V) — footprint constrains to single cap info record open — 2026-06-11
E-028 decision TPS2373 CLSA: 62Ω used instead of 63.4Ω for Class 4 classification info record open — 2026-06-11
E-029 decision TPS2373 CLSB: 91Ω used (equivalent to 90.9Ω) for Class 3 dual-event classification info record open — 2026-06-11
E-030 decision TPS2373 AMPS_CTL: 1kΩ 0603 to VSS — auto-MPS enabled as load supplement info record open — 2026-06-11
E-031 notice TPS2373 PG pin unrouted — GPIOs available for future connection warning next_revision open — 2026-06-11
E-032 notice LM76005 PG pin unrouted — GPIOs available for future connection warning next_revision open — 2026-06-11
E-033 decision JTAG TMS/TDI not swapped in R1 — retain old-product/R0 wiring (reverts E-018/E-019 swap) info record closed — 2026-06-11
E-034 notice JTAG pins 16/18: TDI=GPIO23, TMS=GPIO24 confirmed correct — Group 5 swap was an error warning record closed — 2026-06-11
E-035 decision LM76005 design parameters: feedback, inductor, switching frequency info record open — 2026-06-11
E-036 notice I2C address 0x0C unresolved — verify device and CH224Q address (0x22 vs 0x23) during netlist review info record closed — 2026-06-12
E-037 issue U3 (ECS-3225MV) has wrong EGP in BOM — EGP10000946 belongs to ADS7828 blocking action closed — 2026-06-12
E-038 notice C50 voltage rating marginal — 220µF/6.3V electrolytic on 5V rail warning action closed — 2026-06-12
E-039 notice U17 (LM76005) pins 7 and 23 floating without NC markers info action closed — 2026-06-12
E-040 notice U18 (DS1813R-10) and S3 removed — HRESET_N served no purpose info record closed — 2026-06-12
E-041 issue D3 (DOWO SRV05-4LA) pin 5 is NC by design — not a VRAIL (false alarm) info record closed — 2026-06-12
E-042 notice Schematic R1 out for colleague review — priority focus: M1 RPi pinout & Secondary Power In info record closed — 2026-06-15
E-043 notice ADS7828 (U24) 2 spare ADC channels — connect: board temp (TMP236) + 3V3 monitor info record closed — 2026-06-15
E-044 notice [Accordion M1 R1 — pre-layout schematic walk] Pre-layout schematic+BOM review (board 5, no ODB++ yet). Walked 7 active sheets (1 RPi & Bus,… info record closed — 2026-06-15
E-045 notice U13 (7805) regulates the VIN bus (~21V) down to VCC (5V) — a ~16V linear drop on the always-on rail. Verify before layout: (1) worst-case d… info record closed — 2026-06-15
E-046 notice Layout DRC reviewed (2026-06-15) — no blocking errors; confirm 7 vias-under-SMD-pads before sign-off info record closed — 2026-06-15
E-047 notice J15 (Accordion M2 slot) exposes a VBatt rail (pin 75, fed by a 'VBAT' rail label), but the M1 mainboard has no on-board battery or charger.… info record closed — 2026-06-15
E-048 notice [Accordion M1 R1 — pre-layout review SUMMARY (status of findings)] SUMMARY of the pre-layout schematic+BOM review (board 5, no ODB++). 13 s… info record open — 2026-06-15
E-049 notice ERC-C01: I2CSEL3 (M1-31, GPIO6) and I2CSEL4 (M1-33, GPIO13) are single-pin nets — the signal names imply intended I2C-mux selection bits bu… info record closed — 2026-06-16
E-050 notice ERC-C08: RPi connector pins M1-1 and M1-17 are inconsistent with the recorded pinout table (E-019 / entry 410) which marks both as '3V3 Pow… info record closed — 2026-06-16
E-051 notice ERC-C02: S2 (push-button PBH2UOANAHX) pins 4, 5, 6 are unconnected in the netlist AND lack the (by TERM) marker that every other intentiona… info record closed — 2026-06-16
E-052 notice ERC-D03: PG5 net (TPS259474 U16-3 Power Good output) is pulled up to 3V3 via R68 10k but has no consumer. The pull-up is wired, but no down… info record closed — 2026-06-16
E-053 notice Schematic PDF (ESH10000597_SCH.pdf, 2026-06-15 export) has inconsistent sheet-count footers: sheets 1-8 read 'SHEET X of 12' while sheets 9… info record closed — 2026-06-16
E-054 notice [design-review summary (R1 post-layout take)] DESIGN REVIEW — Accordion M1 R1, post-layout take (ODB++ + BOM + schematic). Verdict: WARNING… info record closed — 2026-06-16
E-055 issue Independent re-verification of the R1 post-layout findings (E-054) — confirms 86/87, finds 1 missed defect: U7.1 floating Schmitt input warning action closed — 2026-06-16
E-056 decision Accordion M1 R1 PCBA ordered at JLCPCB (2026-06-17) — order record + BOM near-misses info record open — 2026-06-18
E-057 notice 1V8 & 2V5 copper routed on GND reference plane — reference-plane discontinuity, defer to R2 warning next_revision open — 2026-06-18
E-058 notice Verify custom-connector LCSC auto-matches J9 / J15 before trusting the order warning action open — 2026-06-18