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E-003 — Fault shutdown uses 74HC00 SR latch with NPN LED driver decision

Created by demo · 2026-06-24

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Decision A 74HC00 NAND-gate SR latch latches the fault state on OVP or OCP trip. An NPN transistor (e.g. BC817) drives the fault LED from the latch Q output. Power cycle clears the latch via a weak pull-down on the RESET line. OVP threshold: Vout_nom + 8% (after tolerance stack-up across all 7 output voltages). ## Rationale The LM5156 EN pin sinks only 1 mA max (datasheet p.14) — insufficient to drive a LED and unreliable as a latch node. A dedicated SR latch from the 74HC00 (already in BOM for voltage selection logic) gives a clean, testable fault path with no interaction with the UVLO startup threshold. ## Rejected alternatives - UVLO pin as fault latch (Option A): Rejected. UVLO threshold shares the same resistor network as the startup voltage, creating a coupling that is hard to characterise across all 7 Vout settings. Also provides no user-visible fault indication without additional circuitry. - PTC self-resetting fuse (Option C): Rejected. Provides OCP protection only, no OVP. Auto-reset behaviour is unsuitable for a bench supply — user expects the fault to latch until they acknowledge it. ## References - Exploration: E-014 - LM5156 datasheet, Table 7.5 (EN pin electrical characteristics)

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