Maestro
Live demo — data resets daily at 03:00 UTC. Nothing you enter is saved.

USB-C PD Multi-Output Boost Supply 100 W

USBPD-MULTI-100W · Rev R0

in_progresselectronics

100 W USB-C PD multi-output boost supply; seven selectable fixed outputs (9/12/15/20/24/48/56 V), discrete-logic control (no MCU). Rebuilt from saved bundle.

Reports Milestones (6)Audit Log

Everything here lives inside a Project (a code + revision, e.g. ESH10000540 R3). The backbone is the V-model, read top-to-bottom: define what the product must do, plan how to prove it, execute the proof on real units, then learn from the field — and the Loop closes back up to the top.
This map is live: a block is green with a count when this project actually has that entity, and dashed/dim when it’s empty. Click any block to open its tab; hover for details. Arrows are the meaningful links; the implicit “belongs to this Project” edge is left out for legibility.

What each thing means

Requirement
One thing the product must do or satisfy — the “what”.
Test Case
A defined check that proves one or more requirements — the “how we prove it”. A verified_by trace link ties a test case to the requirement(s) it covers; that link is exactly what Coverage % counts. (So: a test case refers to the requirements it verifies.)
Verification Plan
A named grouping of test cases, approved before a test campaign and optionally gated by a milestone.
Verification Record
The result of running one test case against one unit: pass / fail / error / na. This is the evidence a requirement is actually met.
DUT
Device Under Test — an individual physical unit (by serial number) that records and test data attach to.
Deviation
A documented waiver against a verification record (e.g. accept a known non-conformance, with justification).
Entry
A knowledge note: a decision (settled choice), notice (assumption / risk / open question), issue (tracked problem), or concept (idea under exploration). It can attach to any other entity.
Design Rule
A reusable, checkable engineering constraint. Running the checks turns each violation into a Conflict.
Conflict
An open flag raised by a failed design-rule check (or an end-of-life / component-library issue) that needs resolving.
Milestone
A dated gate; verification plans can be tied to it.
Field Issue (RMA)
A failure reported from the field on a returned unit; Root-Cause Analysis explains why it happened.
The Loop (S-16)
loop_trace reconciles a field issue against that unit’s own verification record (did it pass at the edge of the band?). closes_loop records the corrective decision or design rule so the lesson is captured — and clears the project’s open-loop count.
Interface / Port
A contract between projects; each port can be driven by a requirement (and cascade one into the connected project).
BOM Component
A part on this project’s bill of materials, optionally linked to the shared Component Library.
GRR Study
A Gauge R&R study measuring how repeatable a test case’s measurement is.
Test Data
Production / Maestro run results recorded against DUTs — the population behind a single verification record.
100% Coverage
94% Done
16 Requirements
26 Test Cases
8 Open Entries

Timeline

Color = derived gate state · hover a tile for its note.
marker
Design Freeze — all open decisions closed, schematic finalised
Jun 24, 2026
marker
Gerber Release — PCB layout complete, thermal sim done, NTC placed
Jul 15, 2026
not started
DVT Gate
Aug 15, 2026· 1/2
marker
First Prototype Bring-up — power-on, PD negotiation, basic output confirmed
Aug 19, 2026
marker
DVT Exit — all test cases and VAL scenarios passed
Sep 23, 2026
marker
Production Release — design package signed off, ready for manufacture
Oct 14, 2026
not started
🏁 Release
· 4/6

Status & gates

Chronological — Release is the final gate. Derived & read-only; edit via trace_milestone_* tools.
MS-001Design Freeze — all open decisions closed, schematic finalised markerdue 2026-06-24
MS-002Gerber Release — PCB layout complete, thermal sim done, NTC placed markerdue 2026-07-15
MS-DVTDVT Gate not started 1/2 metdue 2026-08-15
met Coverage ≥ 80%
  • 16/16 requirements covered (100%)
pending Requirements approved
  • REQ-F-07: draft
  • REQ-N-01: draft
  • REQ-N-03: draft
  • REQ-P-03: draft
MS-003First Prototype Bring-up — power-on, PD negotiation, basic output confirmed markerdue 2026-08-19
MS-004DVT Exit — all test cases and VAL scenarios passed markerdue 2026-09-23
MS-005Production Release — design package signed off, ready for manufacture markerdue 2026-10-14
Release / Readiness not started 4/6 met
pending Requirements approved
  • REQ-F-07: draft
  • REQ-N-01: draft
  • REQ-N-03: draft
  • REQ-P-03: draft
met Coverage ≥ 100%
  • 16/16 requirements covered (100%)
met All test cases pass
  • 25/26 passed
  • 1 accepted deviation(s): VAL-06
met No blocking issues open
met Deviations resolved
pending Interfaces frozen
  • INT-PD: not frozen
Attention 2 open entries

Test Cases

25 Pass 1 Fail / Deviated 0 N/A 0 Open0 / 26 Maestro impl.

Coverage — 100.0% · Done — 93.8%

15 Done 1 Partial 0 Not Started 0 Missing4 Draft0 Obsolete
Entries
8 of 8
CodeKindTitleSeverityScopeStatusMilestoneCreated
E-001 decision Behavioural PWM controller used in simulation instead of LM5156 PSpice model info record open — 2026-06-24
E-002 decision Pure feedforward topology chosen for v8 simulation (no closed-loop control) info record open — 2026-06-24
E-003 decision Fault shutdown uses 74HC00 SR latch with NPN LED driver info record open — 2026-06-24
E-004 concept Output protection and fault-shutdown strategy info record open — 2026-06-24
E-005 concept Voltage selection logic — rotary switch vs DIP switches vs pushbutton cycle info record open — 2026-06-24
E-006 decision Discrete-logic output selection (no MCU) info record open — 2026-06-26
E-007 issue VAL-05: mismatched DIPs (Vin > Vout) pass input through warning action open — 2026-06-26
E-008 notice 56 V rail derates above 45 C ambient info record open — 2026-06-26