USB-C PD Multi-Output Boost Supply 100 W
USBPD-MULTI-100W · Rev R0
100 W USB-C PD multi-output boost supply; seven selectable fixed outputs (9/12/15/20/24/48/56 V), discrete-logic control (no MCU). Rebuilt from saved bundle.
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The backbone is the V-model, read top-to-bottom: define what the product must do, plan how to prove it,
execute the proof on real units, then learn from the field — and the Loop closes back up to the top.
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What each thing means
- Requirement
- One thing the product must do or satisfy — the “what”.
- Test Case
- A defined check that proves one or more requirements — the “how we prove it”. A verified_by trace link ties a test case to the requirement(s) it covers; that link is exactly what Coverage % counts. (So: a test case refers to the requirements it verifies.)
- Verification Plan
- A named grouping of test cases, approved before a test campaign and optionally gated by a milestone.
- Verification Record
- The result of running one test case against one unit: pass / fail / error / na. This is the evidence a requirement is actually met.
- DUT
- Device Under Test — an individual physical unit (by serial number) that records and test data attach to.
- Deviation
- A documented waiver against a verification record (e.g. accept a known non-conformance, with justification).
- Entry
- A knowledge note: a decision (settled choice), notice (assumption / risk / open question), issue (tracked problem), or concept (idea under exploration). It can attach to any other entity.
- Design Rule
- A reusable, checkable engineering constraint. Running the checks turns each violation into a Conflict.
- Conflict
- An open flag raised by a failed design-rule check (or an end-of-life / component-library issue) that needs resolving.
- Milestone
- A dated gate; verification plans can be tied to it.
- Interface / Port
- A contract between projects; each port can be driven by a requirement (and cascade one into the connected project).
- GRR Study
- A Gauge R&R study measuring how repeatable a test case’s measurement is.
- Test Data
- Production / Assert run results recorded against DUTs — the population behind a single verification record.
Plan & time
Allocation grid →Nobody is allocated to this project in the next 8 weeks.
Nothing written for this week yet.
Nobody has written a narrative for this project yet.Timeline
Color = derived gate state · hover a tile for its note.Status & gates
Chronological — Release is the final gate. Derived & read-only; edit viatrace_milestone_* tools.MS-001Design Freeze — all open decisions closed, schematic finalised
overdue / blockeddue 2026-06-24MS-002Gerber Release — PCB layout complete, thermal sim done, NTC placed
overdue / blockeddue 2026-07-15MS-DVTDVT Gate
overdue / blocked
1/2 metdue 2026-08-15
met Coverage ≥ 80%
- 16/16 requirements covered (100%)
pending Requirements approved
- REQ-F-07: draft
- REQ-N-01: draft
- REQ-N-03: draft
- REQ-P-03: draft
MS-003First Prototype Bring-up — power-on, PD negotiation, basic output confirmed
overdue / blockeddue 2026-08-19MS-004DVT Exit — all test cases and VAL scenarios passed
overdue / blockeddue 2026-09-23MS-005Production Release — design package signed off, ready for manufacture
overdue / blockeddue 2026-10-14Release / Readiness not started 4/6 met
pending Requirements approved
- REQ-F-07: draft
- REQ-N-01: draft
- REQ-N-03: draft
- REQ-P-03: draft
met Coverage ≥ 100%
- 16/16 requirements covered (100%)
met All test cases pass
- 25/26 passed
- 1 accepted deviation(s): VAL-06
pending Interfaces frozen
- INT-PD: not frozen
Test Cases
Coverage — 100.0% · Done — 93.8%
| Code | Kind | Title | Severity | Scope | Status | Milestone | Created |
|---|---|---|---|---|---|---|---|
E-001 |
decision | Behavioural PWM controller used in simulation instead of LM5156 PSpice model | info | record | open | — | 2026-06-24 |
E-002 |
decision | Pure feedforward topology chosen for v8 simulation (no closed-loop control) | info | record | open | — | 2026-06-24 |
E-003 |
decision | Fault shutdown uses 74HC00 SR latch with NPN LED driver | info | record | open | — | 2026-06-24 |
E-004 |
concept | Output protection and fault-shutdown strategy | info | record | open | — | 2026-06-24 |
E-005 |
concept | Voltage selection logic — rotary switch vs DIP switches vs pushbutton cycle | info | record | open | — | 2026-06-24 |
E-006 |
decision | Discrete-logic output selection (no MCU) | info | record | open | — | 2026-06-26 |
E-007 |
issue | VAL-05: mismatched DIPs (Vin > Vout) pass input through | warning | action | open | — | 2026-06-26 |
E-008 |
notice | 56 V rail derates above 45 C ambient | info | record | open | — | 2026-06-26 |