USB-C PD Multi-Output Boost Supply 100 W
USBPD-MULTI-100W · Rev R0
in_progresselectronics
100 W USB-C PD multi-output boost supply; seven selectable fixed outputs (9/12/15/20/24/48/56 V), discrete-logic control (no MCU). Rebuilt from saved bundle.
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The backbone is the V-model, read top-to-bottom: define what the product must do, plan how to prove it,
execute the proof on real units, then learn from the field — and the Loop closes back up to the top.
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What each thing means
- Requirement
- One thing the product must do or satisfy — the “what”.
- Test Case
- A defined check that proves one or more requirements — the “how we prove it”. A verified_by trace link ties a test case to the requirement(s) it covers; that link is exactly what Coverage % counts. (So: a test case refers to the requirements it verifies.)
- Verification Plan
- A named grouping of test cases, approved before a test campaign and optionally gated by a milestone.
- Verification Record
- The result of running one test case against one unit: pass / fail / error / na. This is the evidence a requirement is actually met.
- DUT
- Device Under Test — an individual physical unit (by serial number) that records and test data attach to.
- Deviation
- A documented waiver against a verification record (e.g. accept a known non-conformance, with justification).
- Entry
- A knowledge note: a decision (settled choice), notice (assumption / risk / open question), issue (tracked problem), or concept (idea under exploration). It can attach to any other entity.
- Design Rule
- A reusable, checkable engineering constraint. Running the checks turns each violation into a Conflict.
- Conflict
- An open flag raised by a failed design-rule check (or an end-of-life / component-library issue) that needs resolving.
- Milestone
- A dated gate; verification plans can be tied to it.
- Interface / Port
- A contract between projects; each port can be driven by a requirement (and cascade one into the connected project).
- GRR Study
- A Gauge R&R study measuring how repeatable a test case’s measurement is.
- Test Data
- Production / Assert run results recorded against DUTs — the population behind a single verification record.
100%
Coverage
94%
Done
16
Requirements
26
Test Cases
8
Open Entries
Plan & time
Allocation grid →Nobody is allocated to this project in the next 8 weeks.
Latest check-in · Wk 43 2026
Open check-in →
Nothing written for this week yet.
Nobody has written a narrative for this project yet.Timeline
Color = derived gate state · hover a tile for its note.overdue / blocked
Design Freeze — all open decisions closed, schematic finalised
overdue / blocked
Gerber Release — PCB layout complete, thermal sim done, NTC placed
overdue / blocked
DVT Gate
overdue / blocked
First Prototype Bring-up — power-on, PD negotiation, basic output confirmed
overdue / blocked
DVT Exit — all test cases and VAL scenarios passed
overdue / blocked
Production Release — design package signed off, ready for manufacture
not started
🏁 Release
Status & gates
Chronological — Release is the final gate. Derived & read-only; edit viatrace_milestone_* tools.MS-001Design Freeze — all open decisions closed, schematic finalised
overdue / blockeddue 2026-06-24MS-002Gerber Release — PCB layout complete, thermal sim done, NTC placed
overdue / blockeddue 2026-07-15MS-DVTDVT Gate
overdue / blocked
1/2 metdue 2026-08-15
met Coverage ≥ 80%
- 16/16 requirements covered (100%)
pending Requirements approved
- REQ-F-07: draft
- REQ-N-01: draft
- REQ-N-03: draft
- REQ-P-03: draft
MS-003First Prototype Bring-up — power-on, PD negotiation, basic output confirmed
overdue / blockeddue 2026-08-19MS-004DVT Exit — all test cases and VAL scenarios passed
overdue / blockeddue 2026-09-23MS-005Production Release — design package signed off, ready for manufacture
overdue / blockeddue 2026-10-14Release / Readiness not started 4/6 met
pending Requirements approved
- REQ-F-07: draft
- REQ-N-01: draft
- REQ-N-03: draft
- REQ-P-03: draft
met Coverage ≥ 100%
- 16/16 requirements covered (100%)
met All test cases pass
- 25/26 passed
- 1 accepted deviation(s): VAL-06
met
No blocking issues open
met
Deviations resolved
pending Interfaces frozen
- INT-PD: not frozen
Test Cases
25 Pass
1 Fail / Deviated
0 N/A
0 Open0 / 26 Assert impl.
Coverage — 100.0% · Done — 93.8%
| Code | Title | Category | Coverage | Status |
|---|---|---|---|---|
REQ-F-01 |
The unit shall accept a USB-C Power Delivery input of up to 20 V at up to 5 A (100 W total), negotiated via the CH224K PD sink controller. | Functional | Covered | Partial |
REQ-F-02 |
The unit shall provide seven user-selectable fixed output voltages — 9 V, 12 V, 15 V, 20 V, 24 V, 48 V, and 56 V — selected via a 7-position DIP switch that gates individual feedback resistors (Rbot) into the boost converter FB network. | Functional | Covered | Done |
REQ-F-03 |
The unit shall request the desired USB-C PD input voltage (5 V, 9 V, 12 V, 15 V, or 20 V) from the source using the CH224K CFG1/CFG2/CFG3 pins, set by a 3-position DIP switch. No firmware is required. | Functional | Covered | Done |
REQ-F-04 |
On power-up, the unit shall enter standby state with the boost output disabled (output terminals at 0 V) and the blue output LED illuminated. The BTL flip-flop shall power on in the reset state. | Functional | Covered | Done |
REQ-F-05 |
With the override DIP switch off, each press of the run button shall toggle the unit between run (output enabled) and standby (output disabled) states via the BTL D-type flip-flop. The toggle shall be debounced and shall be immune to contact bounce of up to 5 ms. | Functional | Covered | Done |
REQ-F-06 |
When the override DIP switch is set to ON, the external 2-pin terminal (dry contact) shall override the button: shorting the terminal shall enable the output (run); opening the terminal shall disable the output (standby). The button shall have no effect in this mode. | Functional | Covered | Done |
REQ-F-07 |
When the PCB hot-spot temperature exceeds the OT trip threshold, the OTL flip-flop shall latch, disabling the output and illuminating the OT red LED. The latch shall only be cleared (and the unit may then resume run) by a button press after the temperature has fallen below the hysteresis threshold. The unit shall not automatically restart. | Functional | — | — |
REQ-F-08 |
In standby state, the output disconnect switch (Q2 P-FET + Q3 N-FET level shift) shall physically break the inductor/diode conduction path so that the output terminals present true 0 V even with a passive load connected, not merely the residual boost diode drop. | Functional | Covered | Done |
REQ-F-09 |
A bicolour LED shall indicate USB-C PD input status: green when the CH224K has successfully negotiated a PDO (VBUS present and within PG window), red when VBUS is present but negotiation has failed or a fault is detected. | Functional | Covered | Done |
REQ-F-10 |
A tricolour LED shall indicate output state: blue when in standby (RUN=0), green when running and output PG is valid (RUN=1, PG=1), red when running but output PG is not valid (RUN=1, PG=0). Logic: BLUE=!RUN · GRN=RUN·PG · RED=RUN·!PG, implemented via 74HC08/74HC04 gates. | Functional | Covered | Done |
REQ-F-11 |
A dedicated red LED shall be illuminated whenever the OTL latch flip-flop is set (OT event has occurred and has not been cleared). LED shall extinguish when the OTL latch is cleared by button press. | Functional | Covered | Done |
REQ-N-01 |
The unit shall operate within specification across an ambient temperature range of 0 °C to 40 °C at full rated output power. | Environmental | — | — |
REQ-N-02 |
The input connector shall be a USB Type-C receptacle. Power Delivery negotiation shall be implemented using the CH224K PD sink controller in hardware-only mode (CFG pins, no firmware). PD 3.0 protocol shall be supported. | Physical | Covered | Done |
REQ-N-03 |
The output voltage shall be accessible via a user-facing connector. The connector type (screw terminal vs. banana jack) has not yet been decided and depends on the enclosure and front-panel design (see RT-205 and REQ-N-03 OPEN status). Decision drives PCB footprint selection. | Physical | — | — |
REQ-N-04 |
The unit shall provide a 2-pin external control input (dry contact / unpowered switch) that, when the override DIP is enabled, replaces the button for run/standby control. The input shall be immune to external signals up to 1 m of unshielded wire without false triggering. | Physical | Covered | Done |
REQ-P-01 |
The output voltage at any of the seven selectable levels shall remain within ±5 % of the nominal target voltage across the full load range of 10 % to 100 % of rated output power. Verified by load sweep on physical hardware; simulation at 56 V shows ±open-loop offset (closed-loop sim pending LM5156 PSpice model). | Performance | Covered | Done |
REQ-P-02 |
The power conversion efficiency (Pout / Pin) shall be ≥ 90 % at rated output power (100 W). LTspice simulation v7 measured 95.2 % at 20 V in / 56 V out / 32 Ω load. | Performance | Covered | Done |
REQ-P-03 |
The overtemperature protection shall trip at 75 °C ±5 °C measured at the PCB hot-spot NTC. The recovery threshold shall be at least 10 °C below the trip threshold (i.e. ≤ 65 °C). Implemented via NTC + reference divider feeding the LM339 comparator. NTC placement pending PCB layout (RT-207). | Performance | — | — |
REQ-P-04 |
The boost stage shall implement cycle-by-cycle current limiting with a peak current limit of 10 A (set by LM5156 internal threshold). On a persistent output fault (e.g. short circuit), the controller shall enter hiccup mode — repeatedly attempting restart — rather than sustaining a high fault current. Verified behaviourally in LTspice v7 simulation. | Performance | Covered | Done |
REQ-P-05 |
The output power-good (PG) signal shall assert only when the FB node voltage is within ±5 % of the LM5156 reference (nominally 1.25 V), i.e. between 1.1875 V and 1.3125 V. Implemented via fixed-threshold window comparator in LM339 (no output voltage mux needed). | Performance | Covered | Done |