Hypothesis

Since there is no MCU, overcurrent and overvoltage protection must be implemented with discrete logic. The LM5156 has a built-in cycle-by-cycle current limit, but we need a latching shutdown for hard faults and a way to signal the fault state to the user (LED or similar).

Alternatives considered

Option A — LM5156 UVLO pin as fault latch Pull the UVLO pin low via an LM339 comparator when Vout exceeds a threshold. The LM5156 shuts down and stays off until power is cycled.

• Pros: no extra ICs, uses existing comparator bank (LM339 has 4 channels)
• Cons: UVLO threshold interacts with startup — needs careful resistor divider design; hard to distinguish OVP from normal UVLO

Option B — SR latch from 74HC logic Use one 74HC00 NAND gate pair as an SR latch. Comparator trips SET, power cycle clears RESET.

• Pros: clean separation of fault latch from UVLO; easy to add an LED driver from the latch Q output
• Cons: one more IC; requires a weak pull-down on the RESET line to clear on power-up

Option C — Self-resetting PTC + no latch PTC fuse in series with output; temperature-based reset. No latching.

• Pros: dead simple, zero ICs
• Cons: does not protect against OVP, only OCP; reset time unpredictable; not suitable for lab supply (user expects immediate restart after fault removal)

Block diagram (Option B preferred)

graph LR
    Vout --> OVP["LM339 OVP comparator"]
    Isense --> OCP["LM339 OCP comparator"]
    OVP -- SET --> LATCH["74HC00 SR latch"]
    OCP -- SET --> LATCH
    PWRON -- RESET --> LATCH
    LATCH -- Q --> EN["LM5156 EN pin"]
    LATCH -- Q --> LED["Fault LED"]

Open questions

• Does the LM5156 EN pin source enough current to drive a LED directly, or do we need a buffer transistor?
• What is the correct OVP threshold — Vout_set + 10% or Vout_set + 5%? Needs tolerance stack-up analysis.
• For the highest output (56 V), what comparator reference voltage is practical with a single 5 V rail?

Next step

daniel@esharp.se to check LM5156 EN pin sink current spec in datasheet and do a tolerance stack-up for the 56 V OVP threshold.

Hypothesis

The user needs to select one of 7 output voltages (9/12/15/20/24/48/56 V). Since there is no MCU, the selection mechanism must be purely hardware. A multi-position switch drives the 74HC logic that sets the feedback divider ratio.

Alternatives considered

Option A — 8-position rotary switch (preferred) One knob, one pole, 8 positions (7 voltages + off). Direct mechanical encoding.

• Pros: intuitive, single-action selection, no debounce needed for DC logic; 8-position rotary switches are standard (Bourns PRS series, Elma 04 series); maps exactly onto a 74HC138 3-to-8 decoder (8 outputs) with no wasted or undefined states
• Cons: footprint larger than pushbutton

Option B — 4-bit DIP switch bank 4 DIP switches encode 0–15 in binary; only the used states are decoded. 74HC138 decoder maps to the output enables.

• Pros: very common, cheap, no moving parts to wear
• Cons: not intuitive (user must look up binary encoding); can set undefined states; not suited for frequent voltage changes

Option C — Pushbutton cycle (momentary) Single pushbutton steps through voltages in sequence. 74HC163 4-bit counter + reset.

• Pros: minimal panel cutout, elegant
• Cons: requires counter IC, power-cycle resets to first voltage, no direct access to a specific voltage

Position budget note

The earlier concept assumed a 10-position switch for 9 voltages (5/9/12/15/20/24/48/56/60 V) + off. Reducing to an 8-position switch (7 voltages + off) requires dropping two rails. The two natural candidates are 5 V (the boost topology cannot step the USB-C PD input down to 5 V — see open questions) and 60 V (requires LM5156 and output-capacitor voltage ratings plus OVP headroom of ~65 V that is hard to guarantee on a single-stage boost). The remaining 7 rails (9/12/15/20/24/48/56 V) match the project's stated user-selectable set and map exactly onto the 74HC138 3-to-8 decoder.

System block diagram (7 rails + off via 74HC138)

graph LR
    SW["8-pos<br/>rotary switch"] --> DEC["74HC138<br/>decoder"]
    DEC --> R1["R-divider<br/>9 V"]
    DEC --> R2["R-divider<br/>12 V"]
    DEC --> R3["R-divider<br/>15 V"]
    DEC --> R4["R-divider<br/>20 V"]
    DEC --> R5["R-divider<br/>24 V"]
    DEC --> R6["R-divider<br/>48 V"]
    DEC --> R7["R-divider<br/>56 V"]
    R1 & R2 & R3 & R4 & R5 & R6 & R7 --> FB["LM5156<br/>FB pin"]

Open questions

• What is the panel cutout standard for an 8-position rotary? Does it fit the planned enclosure depth?
• Should position 0 (off) cut EN or just set Vout to minimum? Cutting EN is cleaner.
• Do we need a pull-up on the rotary switch outputs to avoid floating inputs during mechanical transition?
• Confirm that dropping the 5 V and 60 V rails to fit the 8-position selector is acceptable, or whether a different pair should be removed instead.

Next step

daniel@esharp.se to confirm enclosure panel depth, 8-position rotary switch body length, and sign off on dropping the 5 V and 60 V rails to fit the 8-position selector.

When DIPs request a voltage below the negotiated PD input, the boost stage passes input through. Needs a guard or a documented limitation.

All 8 LTspice simulation iterations (v1–v8) used a behavioural PWM controller rather than the TI LM5156 PSpice model. This was a deliberate choice for simulation transparency — the behavioural model exposes internal signals (duty cycle, current sense, SR latch) that would be obscured by a vendor model. Consequence: Closed-loop stability (Bode plot, phase margin) has not been verified. The v8 result is a topology demonstrator only, not a production-representative simulation. RT-201 tracks replacement of the behavioural block with the LM5156 PSpice model as a high-priority open item.

After 7 iterations resolving instability, LC-ring at startup, regulation droop, wind-up, and solver convergence issues, v8 settled on pure feedforward with η = 0.95 tuned to match v7 measured efficiency. No closed-loop integrator or error amplifier is present in the current simulation. Consequence: v8 is a topology demonstrator only. Real hardware will use the LM5156 in current-mode control (as specified in ARC-02). The v7 5 V offset at 56 V output is an artefact of η mismatch, not a fundamental limitation of the design.

Decision A 74HC00 NAND-gate SR latch latches the fault state on OVP or OCP trip. An NPN transistor (e.g. BC817) drives the fault LED from the latch Q output. Power cycle clears the latch via a weak pull-down on the RESET line. OVP threshold: Vout_nom + 8% (after tolerance stack-up across all 7 output voltages). ## Rationale The LM5156 EN pin sinks only 1 mA max (datasheet p.14) — insufficient to drive a LED and unreliable as a latch node. A dedicated SR latch from the 74HC00 (already in BOM for voltage selection logic) gives a clean, testable fault path with no interaction with the UVLO startup threshold. ## Rejected alternatives - UVLO pin as fault latch (Option A): Rejected. UVLO threshold shares the same resistor network as the startup voltage, creating a coupling that is hard to characterise across all 7 Vout settings. Also provides no user-visible fault indication without additional circuitry. - PTC self-resetting fuse (Option C): Rejected. Provides OCP protection only, no OVP. Auto-reset behaviour is unsuitable for a bench supply — user expects the fault to latch until they acknowledge it. ## References - Exploration: E-014 - LM5156 datasheet, Table 7.5 (EN pin electrical characteristics)

Seven fixed outputs selected via DIP + discrete logic — avoids firmware certification and simplifies the BOM.

Top rail is thermally limited at high ambient — document in the datasheet.