| 2026-06-04 19:54:09 |
user6@esharp.se |
create |
entry #65 |
api |
show diff
| Field | Before | After |
|---|
| code | — | E-022 | | id | — | 65 | | kind | — | notice | | scope | — | action | | severity | — | blocking | | status | — | open | | title | — | System interface freeze pending sub-module sign-off |
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| 2026-05-27 11:29:40 |
martin.johansson@esharp.se |
update |
test_case #270 |
mcp |
show diff
| Field | Before | After |
|---|
| passCriterion | Measure FE VREF (REF3425, 2.500 V ±0.05 %) at the Sparrow Test Adapter Phoenix terminals P3 (DMM+) / P4 (DMM−) using the external Siglent SDM3055 6½-digit DMM (LAN @ 192.168.0.211:5025 SCPI). Both J5 traces (pin 16 and pin 18) are measured independently — the Test Adapter CD74HC238PWR decoder energises exactly one IME03GR signal relay at a time: RELAY6_DRV (Y4) routes J5 pin 16, RELAY7_DRV (Y5) routes J5 pin 18. Each reading must fall within 2.4987 V .. 2.5013 V (REF3425 ±0.05 % ⊕ TA passive R_on ⊕ SDM3055 1-year DCV uncertainty 0.43 mV @ 2.5 V, RSS).
Distinct from PT-PWR.06 (N-Top VREF_BUF, source-rail spec via onboard ADC) — this test verifies the FE-board REF3425 routed out on J5 and read by an external precision DMM. Implemented by fe_J5_vref.yaml. | Routing-path smoke test for the FE-board REF3425 precision reference (2.500 V ±0.05 % at source) via Sparrow Test Adapter Phoenix terminals P3 (DMM+) / P4 (DMM−) using the external Siglent SDM3055 6½-digit DMM (LAN @ 192.168.0.211:5025 SCPI). Both J5 traces (pin 16 and pin 18) are measured independently — the TA CD74HC238PWR decoder energises exactly one IME03GR signal relay at a time: RELAY6_DRV (Y4) routes J5 pin 16, RELAY7_DRV (Y5) routes J5 pin 18.
**Window: 2.490 V .. 2.510 V** (±10 mV = ±0.4 %) per pin.
**This is a smoke test of the routing path, NOT a precision verification of REF3425.** The Sparrow Test Adapter R0 has no dedicated low-impedance DMM_GND return (J4–J9 GND pins are deliberately routed as signals under test), causing a +5 to +15 mV ground-reference bias on the Phoenix DMM− terminal. The widened window accepts this systemic bias as "routing OK". Diagnostic chain in entry E-007 on project 14; TA R1 fix tracked as a decision entry on the same project.
**Precision verification of REF3425 stays at PT-PWR.06** (N-Top side, via on-board ADC chain — N-Top's AGND *is* the reference there, no ground-offset problem).
**Precondition for the narrowest reading spread (optional):** connect an ad-hoc wire from SDM3055 ground to FE-board AGND. Reduces the bias from ~10 mV to ~3 mV — readings sit near 2.503 V instead of 2.510 V. Without the wire, readings sit near 2.5097 V (still within the widened window).
Implemented by `tests/fe_J5_vref.yaml` in `ESH10000633_SparrowUnitTest_v01`. | | title | FE VREF at J5 (REF3425, 2.5 V) via SDM3055 — both traces | FE VREF at J5 routing-path smoke test via SDM3055 — both traces | | tolerancePct | 0.0500 | 0.4 |
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| 2026-05-27 07:56:39 |
martin.johansson@esharp.se |
create |
test_case #270 |
mcp |
show diff
| Field | Before | After |
|---|
| category | — | Power | | code | — | PT-PWR.10 | | id | — | 270 | | nominal | — | 2.5 | | requirementCode | — | PWR-08 | | signal | — | FE_J5_VREF | | status | — | open | | title | — | FE VREF at J5 (REF3425, 2.5 V) via SDM3055 — both traces | | tolerancePct | — | 0.05 |
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| 2026-05-26 15:41:09 |
martin.johansson@esharp.se |
update |
requirement #67 |
mcp |
show diff
| Field | Before | After |
|---|
| acceptance | Pin inventory per Sparrow Hardware Datasheet v3 §4 (sourceRef: ESH10000633/R1/01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf): J4 — 8 differential AIN channels (AIN_P/N_CH1..8, 16 pins), 5V/12V/GND; J5 — MPIO_0..3 (4), FIXED_LOAD_0..3 (4), TACHO_0..1 (2), PWM_0..1 (2), LATCH_0..1 (2), VREF (1 net, 2 pins), 5V/12V/GND; J6 — MIC_IN_L/~/R/~ (4 pins), LINE_OUT_L/~/R/~ (4 pins), AUDIO_GND (8 pins one net), 5V/12V/GND; J7 — FE_MPIO_0..11 (12), RELAY_1..4 (4), 5V/12V/GND; J8 — VLOAD_POS_0/1, VLOAD_NEG_0/1, VREM_0/1, VPSU_0/1, VSENSE+_0/1, VSENSE-_0/1, 5V/12V/GND; J9 — SCL_SLV, SCL_MSTR, SDA_SLV, SDA_MSTR, EXT_VIO, RS485_RX±, RS485_TX±, 1V8_EXT, 3V3_EXT, 12V_EXT, VADJ, 5V/12V/GND; Audio DSUB-9 — LINE_OUT_L/~/R/~, MIC_IN_L/~/R/~, AUDIO_GND (mirrors J6 nets); Active Load Phoenix — VLOAD_POS_0/1, VREM_0/1, VLOAD_NEG_0/1; PSU Phoenix (optional) — VPSU_0/1, VSENSE+_0/1, VSENSE-_0/1, GND; PoE — PWR, GND. Each functional group above must map to ≥1 PT-* test case; the fixture-electronics-test orchestrator must invoke a sub-test that exercises each group; gaps tracked via please_coverage_gap. | Pin inventory per Sparrow Hardware Datasheet v3 §4 (sourceRef: 01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf): J4 — 8 differential AIN channels (AIN_P/N_CH1..8, 16 pins), 5V/12V/GND; J5 — MPIO_0..3 (4), FIXED_LOAD_0..3 (4), TACHO_0..1 (2), PWM_0..1 (2), LATCH_0..1 (2), VREF (1 net, 2 pins), 5V/12V/GND; J6 — MIC_IN_L/~/R/~ (4 pins), LINE_OUT_L/~/R/~ (4 pins), AUDIO_GND (8 pins one net), 5V/12V/GND; J7 — FE_MPIO_0..11 (12), RELAY_1..4 (4), 5V/12V/GND; J8 — VLOAD_POS_0/1, VLOAD_NEG_0/1, VREM_0/1, VPSU_0/1, VSENSE+_0/1, VSENSE-_0/1, 5V/12V/GND; J9 — SCL_SLV, SCL_MSTR, SDA_SLV, SDA_MSTR, EXT_VIO, RS485_RX±, RS485_TX±, 1V8_EXT, 3V3_EXT, 12V_EXT, VADJ, 5V/12V/GND; Audio DSUB-9 — LINE_OUT_L/~/R/~, MIC_IN_L/~/R/~, AUDIO_GND (mirrors J6 nets); Active Load Phoenix — VLOAD_POS_0/1, VREM_0/1, VLOAD_NEG_0/1; PSU Phoenix (optional) — VPSU_0/1, VSENSE+_0/1, VSENSE-_0/1, GND; PoE — PWR, GND. Each functional group above must map to ≥1 PT-* test case; the fixture-electronics-test orchestrator must invoke a sub-test that exercises each group; gaps tracked via please_coverage_gap. |
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| 2026-05-26 15:41:02 |
martin.johansson@esharp.se |
update |
requirement #66 |
mcp |
show diff
| Field | Before | After |
|---|
| acceptance | Box dimensions 227.00 mm × 129.00 mm × 55.13 mm including the end caps. Per Sparrow Hardware Datasheet v3 §7.2 (sourceRef: ESH10000633/R1/01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) | Box dimensions 227.00 mm × 129.00 mm × 55.13 mm including the end caps. Per Sparrow Hardware Datasheet v3 §7.2 (sourceRef: 01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) |
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| 2026-05-26 15:40:59 |
martin.johansson@esharp.se |
update |
requirement #65 |
mcp |
show diff
| Field | Before | After |
|---|
| acceptance | Board outline 140.0 mm × 80.0 mm; four 3.2 mm through-holes for mounting; maximum installed height ≤ 33.0 mm including bottom components and Active Load (excluding receptacle connectors). Per Sparrow Hardware Datasheet v3 §7.1 (sourceRef: ESH10000633/R1/01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) | Board outline 140.0 mm × 80.0 mm; four 3.2 mm through-holes for mounting; maximum installed height ≤ 33.0 mm including bottom components and Active Load (excluding receptacle connectors). Per Sparrow Hardware Datasheet v3 §7.1 (sourceRef: 01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) |
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| 2026-05-26 15:40:56 |
martin.johansson@esharp.se |
update |
requirement #64 |
mcp |
show diff
| Field | Before | After |
|---|
| acceptance | Short-circuit current limiting + thermal shutdown on TX driver (outputs forced to Hi-Z under fault); TX may be placed in Hi-Z by software for multi-drop handoff; receiver fail-safe bias guarantees logic-HIGH output when input pair is left floating; external 1.1 kΩ pull-ups recommended for improved rise-time. Per Sparrow Hardware Datasheet v3 §6.13 (sourceRef: ESH10000633/R1/01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) | Short-circuit current limiting + thermal shutdown on TX driver (outputs forced to Hi-Z under fault); TX may be placed in Hi-Z by software for multi-drop handoff; receiver fail-safe bias guarantees logic-HIGH output when input pair is left floating; external 1.1 kΩ pull-ups recommended for improved rise-time. Per Sparrow Hardware Datasheet v3 §6.13 (sourceRef: 01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) |
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| 2026-05-26 15:40:52 |
martin.johansson@esharp.se |
update |
requirement #63 |
mcp |
show diff
| Field | Before | After |
|---|
| acceptance | VMEAS_RANGE 0–5 V; VDIFF 1.5–5 V; VCM typ 3 V; data rate ≥ 1 Mbps; gain error ±1.6 %; offset ±6 mV. Per Sparrow Hardware Datasheet v3 §5.2 pages 42–43 and §6.13 (sourceRef: ESH10000633/R1/01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) | VMEAS_RANGE 0–5 V; VDIFF 1.5–5 V; VCM typ 3 V; data rate ≥ 1 Mbps; gain error ±1.6 %; offset ±6 mV. Per Sparrow Hardware Datasheet v3 §5.2 pages 42–43 and §6.13 (sourceRef: 01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) |
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| 2026-05-26 15:40:49 |
martin.johansson@esharp.se |
update |
requirement #62 |
mcp |
show diff
| Field | Before | After |
|---|
| acceptance | Onboard pull-up 10 kΩ on SDA and SCL referenced to EXT_VIO; VDDA_SEL = HIGH when EXT_VIO ≥ 2.5 V, VDDA_SEL = LOW when EXT_VIO ≤ 1.8 V; external 1.1 kΩ pull-ups recommended for high-capacitance / long traces. Per Sparrow Hardware Datasheet v3 §6.12.1 (sourceRef: ESH10000633/R1/01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) | Onboard pull-up 10 kΩ on SDA and SCL referenced to EXT_VIO; VDDA_SEL = HIGH when EXT_VIO ≥ 2.5 V, VDDA_SEL = LOW when EXT_VIO ≤ 1.8 V; external 1.1 kΩ pull-ups recommended for high-capacitance / long traces. Per Sparrow Hardware Datasheet v3 §6.12.1 (sourceRef: 01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) |
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| 2026-05-26 15:40:46 |
martin.johansson@esharp.se |
update |
requirement #61 |
mcp |
show diff
| Field | Before | After |
|---|
| acceptance | VIH min 0.7×EXT_VIO, max 5.5 V; VIL max 0.4 V when EXT_VIO > 2.2 V, otherwise max 0.1×EXT_VIO; VOL when EXT_VIO > 2.2 V: 0.47–0.6 V (typ 0.52 V); VOL when EXT_VIO < 2.4 V: 0.2–0.3 × EXT_VIO. Per Sparrow Hardware Datasheet v3 §5.2 page 41 (sourceRef: ESH10000633/R1/01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) | VIH min 0.7×EXT_VIO, max 5.5 V; VIL max 0.4 V when EXT_VIO > 2.2 V, otherwise max 0.1×EXT_VIO; VOL when EXT_VIO > 2.2 V: 0.47–0.6 V (typ 0.52 V); VOL when EXT_VIO < 2.4 V: 0.2–0.3 × EXT_VIO. Per Sparrow Hardware Datasheet v3 §5.2 page 41 (sourceRef: 01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) |
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| 2026-05-26 15:40:42 |
martin.johansson@esharp.se |
update |
requirement #60 |
mcp |
show diff
| Field | Before | After |
|---|
| acceptance | Minimum RLOAD 1 kΩ; maximum CLOAD 2 nF; resolution 12-bit; IOUT ±5 mA sink/source. Per Sparrow Hardware Datasheet v3 §5.2 pages 38–39 (sourceRef: ESH10000633/R1/01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) | Minimum RLOAD 1 kΩ; maximum CLOAD 2 nF; resolution 12-bit; IOUT ±5 mA sink/source. Per Sparrow Hardware Datasheet v3 §5.2 pages 38–39 (sourceRef: 01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) |
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| 2026-05-26 15:40:38 |
martin.johansson@esharp.se |
update |
requirement #59 |
mcp |
show diff
| Field | Before | After |
|---|
| acceptance | PGA gain settings: 1/8, 1/4, 1/2, 1, 2, 4, 8, 16; PGA accommodates up to ±16 V at input; auto-scaling selects optimal gain; manual gain selection also available for fixed-range cases; PGA855 differential compliance ±17.5 V; common-mode compliance ±15 V. Per Sparrow Hardware Datasheet v3 §6.11, page 50 (sourceRef: ESH10000633/R1/01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) | PGA gain settings: 1/8, 1/4, 1/2, 1, 2, 4, 8, 16; PGA accommodates up to ±16 V at input; auto-scaling selects optimal gain; manual gain selection also available for fixed-range cases; PGA855 differential compliance ±17.5 V; common-mode compliance ±15 V. Per Sparrow Hardware Datasheet v3 §6.11, page 50 (sourceRef: 01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) |
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| 2026-05-26 15:34:31 |
martin.johansson@esharp.se |
update |
requirement #58 |
mcp |
show diff
| Field | Before | After |
|---|
| acceptance | Automatic isolation on overvoltage; protects against miswiring, hot-plugging, and power-sequencing faults; OV tolerance 15 V (per SIG-02 acceptance). Per Sparrow Hardware Datasheet v3 §6.9 note (sourceRef: ESH10000633/R1/01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) | Automatic isolation on overvoltage; protects against miswiring, hot-plugging, and power-sequencing faults; OV tolerance 15 V (per SIG-02 acceptance). Per Sparrow Hardware Datasheet v3 §6.9 note (sourceRef: 01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) |
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| 2026-05-26 15:34:28 |
martin.johansson@esharp.se |
update |
requirement #57 |
mcp |
show diff
| Field | Before | After |
|---|
| acceptance | Pulldown 1 MΩ to GND on every MPIO/FE_MPIO channel. Per Sparrow Hardware Datasheet v3 §6.9 (sourceRef: ESH10000633/R1/01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) | Pulldown 1 MΩ to GND on every MPIO/FE_MPIO channel. Per Sparrow Hardware Datasheet v3 §6.9 (sourceRef: 01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) |
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| 2026-05-26 15:34:25 |
martin.johansson@esharp.se |
update |
requirement #56 |
mcp |
show diff
| Field | Before | After |
|---|
| acceptance | R(AUDIO_GND, system GND) ≤ 1 kΩ. Per Sparrow Hardware Datasheet v3 §6.7 / §6.8 note (sourceRef: ESH10000633/R1/01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) | R(AUDIO_GND, system GND) ≤ 1 kΩ. Per Sparrow Hardware Datasheet v3 §6.7 / §6.8 note (sourceRef: 01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) |
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| 2026-05-26 15:34:23 |
martin.johansson@esharp.se |
update |
requirement #55 |
mcp |
show diff
| Field | Before | After |
|---|
| acceptance | Fast-trip on short-circuit; out-of-regulation flag asserted when feedback loop drops out; thermal shutdown engages before over-temperature damage. Voltage, current, and fault status measured in real time and available to software. Per Sparrow Hardware Datasheet v3 §6.6 (sourceRef: ESH10000633/R1/01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) | Fast-trip on short-circuit; out-of-regulation flag asserted when feedback loop drops out; thermal shutdown engages before over-temperature damage. Voltage, current, and fault status measured in real time and available to software. Per Sparrow Hardware Datasheet v3 §6.6 (sourceRef: 01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) |
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| 2026-05-26 15:34:20 |
martin.johansson@esharp.se |
update |
requirement #54 |
mcp |
show diff
| Field | Before | After |
|---|
| acceptance | Per-port power-limit programmable in software; per-port V and I measurements available to software; PD class detected and reported; disconnect detection and short-circuit protection always active. Per Sparrow Hardware Datasheet v3 §6.5 (sourceRef: ESH10000633/R1/01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) | Per-port power-limit programmable in software; per-port V and I measurements available to software; PD class detected and reported; disconnect detection and short-circuit protection always active. Per Sparrow Hardware Datasheet v3 §6.5 (sourceRef: 01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) |
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| 2026-05-26 15:34:17 |
martin.johansson@esharp.se |
update |
requirement #53 |
mcp |
show diff
| Field | Before | After |
|---|
| acceptance | LED cyan when polarity is normal; magenta when inverted. Polarity may NOT be switched while the load (DUT) is active — accordion reset or Ethernet disconnect required first. Per Sparrow Hardware Datasheet v3 §6.5 (sourceRef: ESH10000633/R1/01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) | LED cyan when polarity is normal; magenta when inverted. Polarity may NOT be switched while the load (DUT) is active — accordion reset or Ethernet disconnect required first. Per Sparrow Hardware Datasheet v3 §6.5 (sourceRef: 01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) |
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| 2026-05-26 15:34:14 |
martin.johansson@esharp.se |
update |
requirement #52 |
mcp |
show diff
| Field | Before | After |
|---|
| acceptance | Class 1–8 compliant per IEEE 802.3af/at/bt; 2-pair and 4-pair modes selectable; operates from external 56 V supply; max combined output 90 W. Per Sparrow Hardware Datasheet v3 §6.5 (sourceRef: ESH10000633/R1/01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) | Class 1–8 compliant per IEEE 802.3af/at/bt; 2-pair and 4-pair modes selectable; operates from external 56 V supply; max combined output 90 W. Per Sparrow Hardware Datasheet v3 §6.5 (sourceRef: 01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) |
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| 2026-05-26 15:34:11 |
martin.johansson@esharp.se |
update |
requirement #51 |
mcp |
show diff
| Field | Before | After |
|---|
| acceptance | SRON output rising slew rate 20 mV/ms (typ); tBleedout discharge time constant ≤ 1 s (first-order RC, τ = R_bleed × C_load). Per Sparrow Hardware Datasheet v3 §5.2 page 33 and §6.2 (sourceRef: ESH10000633/R1/01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) | SRON output rising slew rate 20 mV/ms (typ); tBleedout discharge time constant ≤ 1 s (first-order RC, τ = R_bleed × C_load). Per Sparrow Hardware Datasheet v3 §5.2 page 33 and §6.2 (sourceRef: 01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) |
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| 2026-05-26 15:34:07 |
martin.johansson@esharp.se |
update |
requirement #50 |
mcp |
show diff
| Field | Before | After |
|---|
| acceptance | Transient blanking interval tITIMER ≤ 1.8 ms before shutdown when Ilim ≤ I_load < 2×Ilim; fast-trip when I_load ≥ 2×Ilim; fault flag raised on shutdown; rail stays off until re-enabled. Per Sparrow Hardware Datasheet v3 §5.2 page 33 and §6.2 (sourceRef: ESH10000633/R1/01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) | Transient blanking interval tITIMER ≤ 1.8 ms before shutdown when Ilim ≤ I_load < 2×Ilim; fast-trip when I_load ≥ 2×Ilim; fault flag raised on shutdown; rail stays off until re-enabled. Per Sparrow Hardware Datasheet v3 §5.2 page 33 and §6.2 (sourceRef: 01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) |
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| 2026-05-26 15:34:04 |
martin.johansson@esharp.se |
update |
requirement #49 |
mcp |
show diff
| Field | Before | After |
|---|
| acceptance | Per-pin Ilim 0.25 A (auto-resets via PTC); total Itot ≤ 1.5 A on each rail. Per Sparrow Hardware Datasheet v3 §5.2 page 32 and §6.1 (sourceRef: ESH10000633/R1/01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) | Per-pin Ilim 0.25 A (auto-resets via PTC); total Itot ≤ 1.5 A on each rail. Per Sparrow Hardware Datasheet v3 §5.2 page 32 and §6.1 (sourceRef: 01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf) |
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| 2026-05-26 11:10:33 |
martin.johansson@esharp.se |
create |
verification_record #120 |
mcp |
show diff
| Field | Before | After |
|---|
| dutId | — | | | executionId | — | f51f7fdc-964d-4468-ba38-28d2e8c59440 | | id | — | 120 | | planId | — | | | result | — | pass | | testCaseId | — | 28 |
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| 2026-05-26 11:10:28 |
martin.johansson@esharp.se |
create |
verification_record #119 |
mcp |
show diff
| Field | Before | After |
|---|
| dutId | — | | | executionId | — | f51f7fdc-964d-4468-ba38-28d2e8c59440 | | id | — | 119 | | planId | — | | | result | — | pass | | testCaseId | — | 29 |
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| 2026-05-26 11:10:23 |
martin.johansson@esharp.se |
create |
verification_record #118 |
mcp |
show diff
| Field | Before | After |
|---|
| dutId | — | | | executionId | — | f51f7fdc-964d-4468-ba38-28d2e8c59440 | | id | — | 118 | | planId | — | | | result | — | pass | | testCaseId | — | 94 |
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| 2026-05-26 11:10:18 |
martin.johansson@esharp.se |
create |
verification_record #117 |
mcp |
show diff
| Field | Before | After |
|---|
| dutId | — | | | executionId | — | f51f7fdc-964d-4468-ba38-28d2e8c59440 | | id | — | 117 | | planId | — | | | result | — | pass | | testCaseId | — | 27 |
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| 2026-05-26 11:10:14 |
martin.johansson@esharp.se |
create |
verification_record #116 |
mcp |
show diff
| Field | Before | After |
|---|
| dutId | — | | | executionId | — | f51f7fdc-964d-4468-ba38-28d2e8c59440 | | id | — | 116 | | planId | — | | | result | — | pass | | testCaseId | — | 24 |
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| 2026-05-26 11:10:10 |
martin.johansson@esharp.se |
create |
verification_record #115 |
mcp |
show diff
| Field | Before | After |
|---|
| dutId | — | | | executionId | — | f51f7fdc-964d-4468-ba38-28d2e8c59440 | | id | — | 115 | | planId | — | | | result | — | pass | | testCaseId | — | 93 |
|
| 2026-05-26 11:10:05 |
martin.johansson@esharp.se |
create |
verification_record #114 |
mcp |
show diff
| Field | Before | After |
|---|
| dutId | — | | | executionId | — | f51f7fdc-964d-4468-ba38-28d2e8c59440 | | id | — | 114 | | planId | — | | | result | — | pass | | testCaseId | — | 25 |
|
| 2026-05-26 11:10:00 |
martin.johansson@esharp.se |
create |
verification_record #113 |
mcp |
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| Field | Before | After |
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| 2026-05-26 10:25:48 |
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| category | — | Power | | code | — | PT-PWR.09 | | id | — | 217 | | nominal | — | | | requirementCode | — | PWR-01 | | signal | — | 5V_DIV / 12V_DIV / GND | | status | — | open | | title | — | J4..J9 host-side rail-divider sanity (5V_DIV/12V_DIV/GND) | | tolerancePct | — | |
|
| 2026-05-26 10:09:33 |
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decision #22 |
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| chosenOption | — | Replace the round-number / ±2.5 %-rule windows on `fe_J5_pwm.yaml` with corner-derived limits for STATIC_HIGH and STATIC_LOW. The 50PCT_AVG and ACTUAL_FREQ windows are intentionally wider than the corner (practical PWM averaging effects + gross-fault detection) and are kept.
| Group | Count | Previous YAML | **New YAML** |
|---|---|---|---|
| STATIC_LOW (duty = 0) | 2 | 0.0 – 0.1 V | **−0.01 to +0.05 V (asymmetric)** |
| STATIC_HIGH @ V_SET = 3.3 V | 2 | 3.2175 – 3.3825 V (±2.5 %) | **3.229 – 3.371 V** |
| STATIC_HIGH @ V_SET = 2.5 V | 2 | 2.4375 – 2.5625 V | **2.444 – 2.556 V** |
| STATIC_HIGH @ V_SET = 1.8 V | 2 | 1.7550 – 1.8450 V | **1.758 – 1.842 V** |
| STATIC_HIGH @ V_SET = 1.5 V | 2 | 1.4625 – 1.5375 V | **1.464 – 1.537 V** |
| 50PCT_AVG (duty = 0.5 @ 10 kHz) | 2 | 1.50 – 1.80 V | **1.50 – 1.80 V (kept)** |
| ACTUAL_FREQ_HZ | 2 | 9500 – 10500 Hz | **9500 – 10500 Hz (kept)** |
10 of 14 limit values changed (2 STATIC_LOW + 8 STATIC_HIGH); 4 kept (2 50PCT_AVG + 2 FREQ). | | code | — | D.10 | | id | — | 22 | | rationale | — | ## Chain topology
The PWM test exercises the ATMEGA4809 (U18 on Sparrow N-Top ESH10000535 R3) PWM peripheral outputs. The signals route as a passive pass-through (similar to the J5_FIXED_LOAD and J5_MPIO paths — no 39 Ω + ADG4612 chain, just TVS on the IDC N-Top).
### Per-channel chain
```
[Sparrow N-Top — ESH10000535 R3]
ATMEGA4809 U18 PWM peripheral (PWM_0, PWM_1)
│
(Sparrow N-Top internal routing — pure digital pass-through
to LSHM connectors going to Agent backplane)
│
[FE — Sparrow Fixture Electronics R3]
FE pass-through — no active components on the PWM path
│
[IDC N-Top — ESH10000634 R3]
TVS only (KGSOT05C, reverse-biased, ~nA leakage)
No 39 Ω series R, no ADG4612 switch
│
IDC J5-13 (PWM_0), J5-14 (PWM_1)
│
[TA — Sparrow Test Adapter R0]
J5-13 → routed to host MPIO_18
J5-14 → routed to host MPIO_27
│
[Host AccordionA2 — read via SIG-01 MPIO chain]
Host MPIO is high-impedance (≥1 MΩ pulldown) → V_OH at pad ≈ V_SET (no driver drop)
```
V_SET sweep values come from the EXT_VIO programmable rail (per PWR-07): **1.5, 1.8, 2.5, 3.3 V** — each with ±1.6 % tolerance.
## Tolerance stack
| Source | Tolerance | Reference |
|---|---|---|
| V_SET (EXT_VIO setpoint) | ±1.6 % of set | PLEASE PWR-07 |
| PWM driver V_OH at HiZ | ~V_SET (sub-mV drop) | SIG-04 acceptance ("VOH ≥ 2.9 V @ 3.3 V / 10 mA" — at HiZ load, V_OH ≈ V_SET) |
| PWM driver V_OL at HiZ | ~0 mV | SIG-04 acceptance ("VOL ≤ 0.33 V @ 3.3 V / 10 mA" — at HiZ load, V_OL ≈ 0) |
| Host MPIO gain | ±0.3 % | PLEASE SIG-01 |
| Host MPIO offset | ±8 mV | PLEASE SIG-01 |
| IDC N-Top TVS leakage | ~nA at 25 °C | KGSOT05C datasheet |
| ATmega crystal accuracy | ppm-level (~±0.01 %) | typical 16/20 MHz crystal |
| ATmega PWM duty-cycle resolution | depends on prescaler / TOP value | datasheet (typically 8–16 bit) |
## Corner math — STATIC_HIGH
`V_read = V_SET × (1 ± 0.016) × (1 ± 0.003) ± 0.008 V`
| V_SET | Corner low | Corner high | Window |
|---|---|---|---|
| 3.3 V | 3.3 × 0.984 × 0.997 − 0.008 = **3.229 V** | 3.3 × 1.016 × 1.003 + 0.008 = **3.371 V** | 3.229 – 3.371 V |
| 2.5 V | 2.5 × 0.984 × 0.997 − 0.008 = **2.444 V** | 2.5 × 1.016 × 1.003 + 0.008 = **2.556 V** | 2.444 – 2.556 V |
| 1.8 V | 1.8 × 0.984 × 0.997 − 0.008 = **1.758 V** | 1.8 × 1.016 × 1.003 + 0.008 = **1.842 V** | 1.758 – 1.842 V |
| 1.5 V | 1.5 × 0.984 × 0.997 − 0.008 = **1.464 V** | 1.5 × 1.016 × 1.003 + 0.008 = **1.537 V** | 1.464 – 1.537 V |
These match the previous YAML windows within ~12 mV (current was a flat ±2.5 % formula slightly wider than the corner at higher V_SET, essentially identical at 1.5 V). Tightening to corner-match catches small drift without losing real-fault sensitivity.
## Corner math — STATIC_LOW
V_OL at HiZ load is essentially 0 mV (no current to drop voltage across the PWM driver's pulldown). With MPIO offset ±8 mV:
- Worst-low reading: −8 mV (ADC offset only; driver can't drive negative)
- Worst-high reading: +50 mV (allows ~40 mV V_OL margin for partial-conduction faults + ±8 mV offset)
YAML window → **−0.01 to +0.05 V** (rounded outward).
Previous 0.0 – 0.1 V window allowed up to +100 mV which is wider than the corner. Tightening to +0.05 V catches a stuck-mid or partially-conducting PWM driver earlier.
## 50PCT_AVG and ACTUAL_FREQ — kept
### 50PCT_AVG (duty = 0.5 @ 10 kHz, V_SET = 3.3 V)
Nominal V_avg = V_SET / 2 = **1.65 V**. Chain corner (assuming exact 50 % duty): 1.59 – 1.71 V (±60 mV).
YAML window 1.50 – 1.80 V (±150 mV) is intentionally wider — accommodates:
- **PWM ripple residue** at the host MPIO (10 kHz fundamental + harmonics, partial RC filtering)
- **Duty-cycle quantization** in the ATmega PWM peripheral (depending on prescaler / TOP value, exact 50 % may be off by half-LSB)
- **Integration-window mismatch** between the host sampling and the PWM period
These practical effects aren't easily corner-derived from datasheet specs. The wide window is appropriate for this measurement. **Kept.**
### ACTUAL_FREQ_HZ
Crystal-based ATmega is ppm-accurate; the actual reading should be 10000 ± 1 Hz on a healthy unit. The YAML's ±5 % window (9500 – 10500 Hz) is intentionally generous — it's a **gross-fault detector**: catches "peripheral didn't initialise", "register write missed", "wrong PWM channel selected", "PWM not enabled", etc. **Kept.**
## Source documents
- Sparrow N-Top PCBA ESH10000535 R3 — BOM (`PartsList_Sparrow_NTop_R3.csv`): U18 = ATMEGA4809 (EGP10001000) for PWM/Tach peripheral
- Sparrow Fixture Electronics ESH10000540 R3 — pass-through for PWM signals
- Sparrow IDC N-Top ESH10000634 R3 — netlist: PWM_0/PWM_1 route through KGSOT05C TVS only (no 39 Ω, no ADG4612)
- Sparrow Test Adapter ESH10000654 R0 — routes J5-13 → host MPIO_18, J5-14 → host MPIO_27
- PLEASE SIG-04 — PWM 2-channel spec: 1 Hz – 1 MHz; duty 0–100 %; VCCO 0–3.3 V; V_OH ≥ 2.9 V @ 3.3 V / 10 mA; V_OL ≤ 0.33 V @ 3.3 V / 10 mA
- PLEASE PWR-07 — EXT_VIO programmable rail: 0–3.3 V, ±1.6 % of set
- PLEASE SIG-01 — host MPIO chain accuracy: ±0.3 % gain, ±8 mV offset
- ATMEGA4809 datasheet (EGP10001000) — PWM peripheral spec, crystal-based timing | | title | — | fe_J5_pwm.yaml limit derivation — ATMEGA4809 PWM through HiZ MPIO read at 4 V_SET levels | | tradeOffs | — | ## Tradeoffs accepted
### STATIC_HIGH tightened from ±2.5 % flat formula to corner-derived
- **Previous flat ±2.5 % window was slightly wider than the corner** at higher V_SET (e.g. at 3.3 V the YAML was ±82.5 mV vs corner ±71 mV). The extra margin had no derivation behind it.
- **New corner-derived windows match the ±1.6 % rail ⊕ MPIO chain corner exactly.** Catches:
- Wrong V_SET rail selected (e.g. 1.8 V rail used when 2.5 V expected) — caught (way outside any setpoint window)
- Rail at spec edge passes correctly
- PWM driver permanently low or floating (V_read ≈ 0 V or pull) — caught
- Subtle drift just outside ±1.6 % rail spec or ±0.3 % MPIO gain — caught
- **Difference from previous**: ~12 mV per side at 3.3 V down to ~1 mV per side at 1.5 V. Small in absolute terms but represents the actual chain corner.
### STATIC_LOW tightened from 0.0–0.1 V to −0.01/+0.05 V (asymmetric)
- **Previous 0.0 – 0.1 V allowed up to 100 mV** — much wider than the physical corner. A PWM driver that's stuck at ~80 mV (partial conduction, leaky output stage, soft short to a small bias network) would pass the old window.
- **New −0.01 to +0.05 V matches the corner**: ADC offset can produce negative readings (bound at −8 mV), driver V_OL at HiZ should be at most a few mV (well within +50 mV).
- **Asymmetric**: low bound at −0.01 (just past ADC offset) instead of 0.0, since the physical V can't go negative — only measurement offset can.
### 50PCT_AVG kept at ±9 % window
- **Practical PWM-averaging effects dominate the measurement.** Tightening to the chain corner (±60 mV) would risk nuisance fails from:
- Imperfect filtering of 10 kHz ripple at the host MPIO (RC time constant must be ≫ PWM period for clean averaging)
- ATmega PWM duty-cycle quantization (8-bit timer at 10 kHz with 16 MHz clock gives ~6-bit effective duty resolution, so duty=50 % might actually be 49–51 %)
- Sampling-window vs PWM-period mismatch
- **Future tightening possible** with empirical SPC data. If production runs show a tight distribution at exactly 1.65 V ± 30 mV, the window could shrink to e.g. 1.55 – 1.75 V.
### ACTUAL_FREQ kept at ±5 % window
- **The window is for gross-fault detection, not parametric drift.** Crystal-based ATmega is ppm-accurate; any healthy reading is 10000 ± 1 Hz.
- A reading outside ±5 % indicates a real systemic failure: peripheral didn't initialise, register write missed, wrong PWM channel enabled, oscillator failed.
- Tightening to ±0.1 % (still very generous vs crystal accuracy) would be a meaningful upgrade — but the ±5 % gross-fault catch is already doing what the test needs.
- **Future tightening to ±0.1 %** worth considering if a frequency-drift mode is ever a real failure mode worth catching.
### V_SET assumed to be EXT_VIO
- The YAML comment doesn't explicitly state which rail provides V_SET = 1.5 / 1.8 / 2.5 / 3.3 V. I assumed **EXT_VIO** (PWR-07) because these are exactly the EXT_VIO sweep setpoints. If V_SET is actually a different rail (e.g. ATmega's own VCC), tolerance would differ:
- EXT_VIO: ±1.6 % per PWR-07 (used here)
- ATmega VCC if 3.3 V system rail: ±5 % typically — would make the window much wider
- **Assumption is the natural one** given the EXT_VIO sweep is the only test infrastructure that produces those exact setpoints in production. Verify by checking the Python runner module.
### Outward rounding choices
- STATIC_HIGH limits use 3-decimal precision (±1 mV) matching the corner exactly. No outward rounding margin since the corner already accounts for worst-case spec.
- STATIC_LOW upper bound 0.05 V chosen as a "catch partial-conduction faults" practical threshold rather than strictly corner-derived (corner says < 0.01 V).
## Follow-up actions
1. ~~Update YAML limits~~ — done (10 of 14 windows changed; 4 kept).
2. ~~Document derivation~~ — done (this decision).
3. **TODO:** Verify V_SET sweep source in `fe_J5_pwm.py` runner. Confirm V_SET = EXT_VIO (the assumption underlying the ±1.6 % tolerance). If V_SET comes from a different rail with different tolerance, the STATIC_HIGH windows need adjustment.
4. **TODO:** After ≥10 production runs through `fe_J5_pwm`, pull SPC stats:
- STATIC_HIGH at each V_SET — confirm Cpk ≥ 1.33 within the new (corner-tight) windows.
- 50PCT_AVG — measure typical spread. If it's tight (e.g. ±30 mV), consider tightening the YAML window to match.
- ACTUAL_FREQ — confirm readings cluster at 10000 ± 1 Hz. Consider tightening to ±100 Hz (still 10× the typical spread) for better fault sensitivity.
5. **TODO:** Capture ATMEGA4809 (EGP10001000) in PLEASE via `please_component_update` with PWM peripheral specs (duty resolution, frequency accuracy from crystal).
6. **TODO:** Cross-reference D.10 from any PLEASE test case (PT-SIG-04.*) that maps to a `pt_code` tag in `fe_J5_pwm.yaml`. |
|
| 2026-05-26 10:01:24 |
martin.johansson@esharp.se |
create |
decision #21 |
mcp |
show diff
| Field | Before | After |
|---|
| chosenOption | — | Replace the round-number loopback windows on `fe_J5_mpio.yaml` with corner-derived limits — same SIG-01 / chain corner math as `fe_J7_mpio_relay.yaml` Step 1 (D.07). The drive-4 V and drive-0.5 V windows were tighter than the DAC + ADC compounded chain can guarantee; INIT and crosstalk windows already match their corner / practical limit and are kept.
| Group | Count | Previous YAML | **New YAML** |
|---|---|---|---|
| INIT (idle, expect 0 V) | 4 | −0.01 to +0.01 V | **−0.01 to +0.01 V (kept)** |
| Drive 4 V → partner reads | 4 | 3.98 – 4.02 V | **3.96 – 4.04 V** |
| Drive 0.5 V → partner reads | 4 | 0.49 – 0.51 V | **0.48 – 0.52 V** |
| Crosstalk (other 2 channels while 4 V driven) | 8 | ±0.1 V | **±0.1 V (kept)** |
8 limit values changed (4 drive-4V + 4 drive-0.5V), 12 kept. | | code | — | D.09 | | id | — | 21 | | rationale | — | ## Chain topology (full path traced from netlists)
The J5 MPIO test exercises the AD5592R on the Sparrow N-Top (ESH10000535 R3) — **not** the FE-side AD5593Rs (which `fe_J7_mpio_relay.yaml` covers). The signals route as a passive pass-through across three boards plus the TA loopback.
### Per-channel chain
```
[Sparrow N-Top — ESH10000535 R3]
AD5592R (U10 or U22, 12-bit DAC/ADC, EGP10000891)
DAC channel (one of IO0..IO7)
│
(Sparrow N-Top internal routing — may include PS509LEX
analog mux U2/U3/U12/U25; R_DS_on ~150 Ω, sub-mV at HiZ ADC)
│
→ Agent backplane → AccordionA2 host
│
[FE — Sparrow Fixture Electronics R3]
J10 LSHM pin (Agent-facing, EGP10001595 LSHM-120):
pin 13 ↔ MPIO_1, pin 14 ↔ MPIO_3,
pin 15 ↔ MPIO_0, pin 16 ↔ MPIO_2
│
── wire pass-through (no active components, no series R) ──
│
J2 LSHM pin (IDC-N-Top-facing, EGP10001411 AXK5S60047):
pin 21 ↔ MPIO_0, pin 22 ↔ MPIO_1,
pin 23 ↔ MPIO_2, pin 24 ↔ MPIO_3
│
[IDC N-Top — ESH10000634 R3]
J2 LSHM pin (21..24)
│
D9 / D10 KGSOT05C TVS to GND (ESD only, reverse-biased ~nA leakage)
│ (NO 39 Ω series R, NO ADG4612 switch on this path —
│ unlike FE_MPIO_2..11 which DO go through that chain.)
│
IDC J5 pin: 3 (MPIO_0), 5 (MPIO_1), 7 (MPIO_2), 9 (MPIO_3)
│
[TA — Sparrow Test Adapter R0]
J5-3 ↔ J5-7 (MPIO_0 ↔ MPIO_2 loopback short)
J5-5 ↔ J5-9 (MPIO_1 ↔ MPIO_3 loopback short)
(NO pullup, NO load, NO divider — just the shorts)
```
### Test sequence (per pair, e.g. 0↔2)
1. Configure MPIO_0 as DAC, drive 4.0 V (or 0.5 V).
2. Configure MPIO_2 as ADC, read back. (= `*_A_4V_B` / `*_A_0V5_B`)
3. Configure MPIO_1 and MPIO_3 as ADC, read crosstalk while 4 V is held.
4. Swap roles: MPIO_2 drives, MPIO_0 reads. (= `*_B_4V_A` / `*_B_0V5_A`)
## Tolerance stack
| Source | Tolerance | Reference |
|---|---|---|
| AD5592R DAC gain | ±0.3 % | PLEASE SIG-01 (chain-level spec) |
| AD5592R DAC offset | ±8 mV | SIG-01 |
| AD5592R ADC gain | ±0.3 % | SIG-01 |
| AD5592R ADC offset | ±8 mV | SIG-01 |
| Sparrow N-Top PS509LEX analog mux R_DS_on (if in path) | ~150 Ω typ, ~200 Ω worst | TI datasheet |
| FE wire pass-through | < 0.1 Ω | trace |
| IDC N-Top TVS leakage | ~nA at 25 °C, ~µA at 85 °C | KGSOT05C datasheet |
The DAC and ADC errors compound (independent error sources, even though both are on the same AD5592R chip — different channels, different gain/offset paths). Vref drift cancels in loopback.
**Passive chain elements (TVS, PS509LEX, ribbon) contribute sub-mV at HiZ ADC current**, dominated by the AD5592R DAC + ADC accuracy.
## Corner math
`V_read = V_set × DAC_gain × ADC_gain ± DAC_offset ± ADC_offset`
Combined chain: gain ±0.6 %, offset ±16 mV (worst case, sequential).
### Drive 4.0 V
| Corner | V_set | × gain | ± offset | V_read |
|---|---|---|---|---|
| Worst-low | 4.0 V | × 0.994 | − 0.016 | **3.960 V** |
| Nominal | 4.0 V | × 1.000 | 0 | 4.000 V |
| Worst-high | 4.0 V | × 1.006 | + 0.016 | **4.040 V** |
YAML window → **3.96 – 4.04 V**.
### Drive 0.5 V
| Corner | V_set | × gain | ± offset | V_read |
|---|---|---|---|---|
| Worst-low | 0.5 V | × 0.994 | − 0.016 | **0.481 V** |
| Worst-high | 0.5 V | × 1.006 | + 0.016 | **0.519 V** |
YAML window → **0.48 – 0.52 V**.
### INIT (idle)
DAC at 0 V (or HiZ + pulldown chain). ADC reads with its own offset only — DAC contribution at 0 V is 0 V × gain = 0. Worst-case ±8 mV (SIG-01 offset). Current YAML ±0.01 V matches with 2 mV margin. **Kept.**
### Crosstalk (other 2 channels read while 4 V is driven on one channel)
Physical DC crosstalk between MPIO channels through the ribbon-cable parasitic R is sub-mV (each channel has its own DAC drive and ADC read; no shared current path). The ±0.1 V window allows for AC capacitive coupling during the drive transient + a wide margin. **Kept.**
## Difference from D.07 (fe_J7_mpio_relay Step 1)
D.07 and D.09 produce **identical windows** because the loopback chain shape is the same (DAC → passive → loopback short → passive → ADC). The differences are:
| Aspect | D.07 (fe_J7_mpio_relay) | D.09 (fe_J5_mpio) |
|---|---|---|
| Source of MPIO channels | FE's AD5593R U5, U6 | Sparrow N-Top's AD5592R U10/U22 |
| Path through IDC N-Top | 39 Ω + ADG4612 + TVS | **TVS only** (no 39 Ω, no ADG4612) |
| Loopback location | IDC J7 pins on TA | IDC J5 pins on TA |
| Number of channels | 12 (FE_MPIO_0..11) | 4 (MPIO_0..3) |
| Pair config | 4 pairs (0↔2, 1↔3, 4↔6, 5↔7) | 2 pairs (0↔2, 1↔3) |
The chain accuracy spec (SIG-01 per direction) is the same, so the corner windows are the same.
## Source documents
- Sparrow N-Top PCBA ESH10000535 R3 — BOM (`PartsList_Sparrow_NTop_R3.csv`): U10, U22 = AD5592R (EGP10000891)
- Sparrow Fixture Electronics ESH10000540 R3 — netlist (`NetList_Sparrow_FE_R3.qcv`): MPIO_0..3 = J10-15/13/16/14 (Agent) ↔ J2-21/22/23/24 (IDC N-Top), pure wire pass-through
- Sparrow IDC N-Top ESH10000634 R3 — netlist (`NetList_Sparrow_FE_N-Top_R3.qcv`): J2-21..24 ↔ J5-3/5/7/9 via D9/D10 KGSOT05C TVS only
- Sparrow Test Adapter ESH10000654 R0 — schematic shows J5-3↔J5-7 and J5-5↔J5-9 loopback shorts (no pullup, no load on the J5 MPIO pins)
- PLEASE SIG-01 — MPIO 4-channel chain accuracy: ±0.3 % gain, ±8 mV offset
- PLEASE D.07 — same shape derivation for FE_MPIO loopback (Step 1) | | title | — | fe_J5_mpio.yaml limit derivation — AD5592R loopback chain (Sparrow N-Top → FE pass-through → IDC N-Top → TA) | | tradeOffs | — | ## Tradeoffs accepted
### Drive 4 V / 0.5 V windows widened to chain corner
- **Previous 3.98–4.02 / 0.49–0.51 V windows were half the chain corner.** Same root cause as D.07: the assumption that single-direction SIG-01 accuracy applies to a loopback read is wrong. The DAC contribution + ADC contribution compound.
- **New windows match the corner exactly.** Catches:
- Open DAC channel (V_read = 0 V or rail) — easily flagged
- Failed TA loopback short (V_read = floating, typically rail or driven by leakage) — flagged
- DAC stuck at wrong code — caught
- Pure linearity / offset drift within SIG-01 spec — passes correctly
### INIT, crosstalk kept
- Already at SIG-01 offset bound (±0.01 V) and practical capacitive-coupling allowance (±0.1 V) respectively. No reason to change.
### Sparrow N-Top PS509LEX analog mux not modelled explicitly
- I noted in the chain that the Sparrow N-Top internal routing **may include** PS509LEX analog mux switches between the AD5592R and the output connector. The R_DS_on of PS509LEX (~150–200 Ω) is in series with the channel, but at the loopback partner's HiZ ADC input, no current flows → sub-mV drop → doesn't affect DC accuracy.
- **Did not trace the Sparrow N-Top schematic in detail.** If the N-Top has additional series elements (e.g. ESD diodes, attenuators) that DO affect DC, the windows would need adjustment. Will revisit if production data shows systematic offset.
### Same chain corner as D.07 → same window
- D.09's drive-4V window (3.96–4.04 V) is identical to D.07's. **Production SPC implication**: both tests should show similar distributions on healthy units. If one test passes 4.0 V loopback and the other consistently fails, the issue is in the test-specific chain (Sparrow N-Top vs FE AD5593R), not in the AD5592R/AD5593R DAC/ADC accuracy itself.
### What this test doesn't catch
- **PS509LEX stuck OFF on the Sparrow N-Top.** If PS509LEX is in the path and gets stuck OFF, the loopback would fail entirely (DAC drive doesn't reach the J5 pin → reading floats). The test would catch this as a wildly out-of-window reading, but wouldn't distinguish "PS509LEX stuck" from "DAC stuck" from "loopback short broken". Diagnosis requires probing the Sparrow N-Top output pins directly.
- **Sparrow N-Top to Agent connector contact issues.** Same as above: any break in the path produces an out-of-window reading but doesn't tell you where.
## Follow-up actions
1. ~~Update YAML limits~~ — done (8 of 20 windows changed; 12 kept).
2. ~~Document derivation~~ — done (this decision).
3. **TODO:** Trace the Sparrow N-Top schematic in detail — confirm whether MPIO_0..3 from AD5592R route through PS509LEX, and if so, document the per-channel R_DS_on contribution. Capture the AD5592R (EGP10000891) and PS509LEX (EGP10001572) in PLEASE via `please_component_update` with structured properties.
4. **TODO:** After ≥10 production runs through `fe_J5_mpio`, pull SPC stats:
- Drive 4 V Cpk ≥ 1.33 within 3.96–4.04 V.
- Drive 0.5 V Cpk ≥ 1.33 within 0.48–0.52 V.
- Compare distribution to `fe_J7_mpio_relay` Step 1 (FE_MPIO_0..7 loopback). Significant systematic offset between the two would indicate either chip-family difference (AD5592R vs AD5593R) or unmodelled chain element (e.g. PS509LEX).
5. **TODO:** Cross-reference D.09 from any PLEASE test case (PT-SIG-01.*) that maps to a `pt_code` tag in `fe_J5_mpio.yaml`. |
|
| 2026-05-26 09:37:18 |
martin.johansson@esharp.se |
create |
decision #20 |
mcp |
show diff
| Field | Before | After |
|---|
| chosenOption | — | Replace the round-number windows on `fe_J5_fixed_load.yaml` with corner-derived limits accounting for the FE-side 200 K VMEAS divider's loading on the TA 2.2 K pullup.
| Group | Count | Previous YAML | **New YAML** |
|---|---|---|---|
| Open switch — pullup only at J5 pin (default + 3 other channels per scenario) | 16 | 2.40 – 2.60 V | **2.35 – 2.61 V** |
| Closed switch — pullup + load divider | 4 | 1.15 – 1.35 V | **1.17 – 1.33 V** |
Also corrected the YAML inline comment that said "1.25 V midpoint" / "full 2.5 V" — the actual nominals are **1.24 V** and **2.47 V** because the FE-side VMEAS divider (100 K + 100 K to GND = 200 K parallel load) shifts the pullup voltage down by ~1 %. | | code | — | D.08 | | id | — | 20 | | rationale | — | ## Chain topology
The fixed-load test exercises 4 NMOS switches on the FE that pull each J5 channel toward GND through a 2.2 kΩ FE-side resistor. The TA pullup (2.2 kΩ to 2.5 V) sets the open-state voltage; the FE VMEAS divider (100 K + 100 K) reads the J5 pin through a passive ÷2 attenuator. Software multiplies the ADC reading by 2 to report V_pin.
### Per-channel chain
```
[TA — Sparrow Test Adapter R0]
2.5 V (AMS1117)
│
R11..R14 (2.2 kΩ ±1 %) ← TA pullup
│
J5 IDC pin (4 / 6 / 8 / 10)
[N-Top — Sparrow IDC N-Top R3]
J5 IDC pin
│
D15 / D16 KGSOT05C TVS to GND ← ESD only, reverse-biased ~nA leakage
│
LSHM J2 pin (31 / 32 / 33 / 34)
│
FE J2 pin
[FE — Sparrow Fixture Electronics R3]
FE J2-31..34 (= GND_SW0..3_OUT)
│
├── R175..R178 (2.2 kΩ 1 %) ─ Q4/Q5 2N7002DW drain ─ source ─ GND
│ (gate ← GND_SW0..3 from PCA9506 I/O expander, 3.3 V logic)
│ (R_DS_on ~5 Ω typ, ~10 Ω worst at V_GS = 3.3 V)
│
└── R235..R238 (100 K 1 %, VMEAS divider top)
│
mid
├── R241..R244 (100 K 1 %, bot) ─ GND
└── R267..R270 (120 Ω LP) ─ ADS7828EB U40 ch4..7
(ADC ×0.5 attenuator;
software ×2 back to V_pin)
```
**Key topology note**: unlike the FE_MPIO test, the N-Top does **not** insert a 39 Ω + ADG4612 switch on these lines — only a TVS for ESD. So the path from TA to FE is essentially direct (modulo ribbon-cable resistance < 0.1 Ω, negligible).
## Equivalent circuit at the J5 pin
| State | R_FE_load (to GND) | R_VMEAS (to GND) | R_loading_parallel |
|---|---|---|---|
| Open switch (Q4/Q5 OFF) | ∞ (HiZ drain) | 200 K (100 K + 100 K) | **200 K** |
| Closed switch (Q4/Q5 ON) | 2.2 K + R_DS_on ≈ 2.21 K | 200 K | (2.21 K) \|\| 200 K = **2.18 K** |
With R_TA_pullup = 2.2 K to V_TA, the divider equation is:
```
V_pin = V_TA × R_loading / (R_TA + R_loading)
```
## Corner math
### Open switch (16 measurements)
`V_pin = V_TA × 200 / (2.2 + 200) = V_TA × 0.9891`
| Corner | V_TA | × loading ratio | V_pin (raw) | × VMEAS chain (SIG-07: ±1.6 % gain, ±6 mV offset) | V_reported |
|---|---|---|---|---|---|
| Worst-low | 2.425 V | × 0.9891 | 2.398 V | × 0.984 − 0.006 | **2.354 V** |
| Nominal | 2.500 V | × 0.9891 | 2.473 V | × 1.000 | 2.473 V |
| Worst-high | 2.588 V | × 0.9891 | 2.560 V | × 1.016 + 0.006 | **2.607 V** |
YAML window → **2.35 – 2.61 V** (rounded outward to 1 cV).
**Nominal is 2.47 V, not 2.5 V.** This 27 mV downshift from "expected 2.5 V" is the 200 K parallel load on the 2.2 K pullup — about 1 % loss. Critical for production SPC: the open-switch distribution should centre at ~2.47 V; readings outside 2.35–2.61 V indicate real fault (loose TA connection, FE VMEAS short, broken pullup, etc.).
### Closed switch (4 measurements)
`R_par = (R_FE + R_DS_on) || R_VMEAS = (~2.21 K) || (~200 K) ≈ 2.18 K`
`V_pin = V_TA × R_par / (R_TA + R_par)`
| Corner | V_TA | R_par | V_pin (raw) | × VMEAS chain | V_reported |
|---|---|---|---|---|---|
| Worst-low | 2.425 V | 2.16 K (R_FE_low ‖ R_VMEAS_low) | 1.195 V | × 0.984 − 0.006 | **1.170 V** |
| Nominal | 2.500 V | 2.18 K | 1.244 V | × 1.000 | 1.244 V |
| Worst-high | 2.588 V | 2.21 K (R_FE_high ‖ R_VMEAS_high) | 1.302 V | × 1.016 + 0.006 | **1.329 V** |
YAML window → **1.17 – 1.33 V** (rounded outward).
**Nominal is 1.24 V, not 1.25 V.** The 200 K VMEAS divider's small contribution to the bottom-side resistance pulls the midpoint down by ~6 mV from the "pure" 2.2 K + 2.2 K = 1.25 V centre. Negligible in absolute terms but should be reflected in SPC expectations.
## Source documents
- Sparrow FE PCBA ESH10000540 R3 — schematic page 6 (Fixed Load + UART-RS485):
- Q4, Q5 = 2N7002DW (EGP10000893) dual NMOS
- R175..R178 = 2.2 kΩ 1 % (EGP10000081) — FE load resistors (gate-controlled)
- R235..R238 = 100 K 1 % (EGP10000121) — VMEAS divider top
- R241..R244 = 100 K 1 % (EGP10000121) — VMEAS divider bottom
- R267..R270 = 120 Ω 1 % (EGP10000052) — LP filter to ADC
- U40 = ADS7828EB (EGP10000946) — 12-bit ADC, ch4..7 used for fixed-load VMEAS
- U7 = PCA9506BS (EGP10001232) — I/O expander, 3.3 V logic, drives GND_SW0..3
- Sparrow IDC N-Top PCBA ESH10000634 R3 — netlist `NetList_Sparrow_FE_N-Top_R3.qcv`:
- LSHM J2-31..34 ↔ IDC J5-4/6/8/10
- D15, D16 = KGSOT05C TVS only (no 39 Ω, no ADG4612 on this path)
- Sparrow Test Adapter ESH10000654 R0 — schematic:
- R11..R14 = 2.2 kΩ 1 % (EGP10000081) — TA pullup to 2.5 V
- U3 = AMS1117-ADJ (EGP10001062) — 2.5 V rail source (per D.03)
- PLEASE SIG-07 — fixed-load VMEAS chain spec: gain ±1.6 %, offset ±6 mV
- PLEASE D.03 — AMS1117 V_pullup tolerance (+3.5 % / −3.0 %) | | title | — | fe_J5_fixed_load.yaml limit derivation — TA pullup + FE GND_SW + 200 K VMEAS-divider loading | | tradeOffs | — | ## Tradeoffs accepted
### Open-switch window widened from ±0.10 V to a corner-fit ±0.13 V (asymmetric: 2.35–2.61 V)
- **Previous 2.40 – 2.60 V was too tight.** At worst-low corner (V_TA = 2.425 V × 0.989 loading × 0.984 VMEAS gain − 0.006 offset = 2.354 V), a healthy unit at the AMS1117 floor + VMEAS spec edge would nuisance-fail. At worst-high (2.607 V), same problem on the upper bound.
- **New 2.35 – 2.61 V matches the corner exactly.** Catches:
- Broken / missing TA pullup (V_pin → 0 V or floating ~ random) — caught
- FE VMEAS shorted to GND (V_pin reads 0 V) — caught
- Pullup-to-5 V short (V_pin reads ~5 V) — caught
- Stuck FE NMOS ON (V_pin reads ~1.24 V) — caught (below 2.35 V floor)
- Pure spec-edge drift (in-tolerance components) — passes correctly
### Closed-switch window tightened from ±0.10 V to ±0.08 V (1.17–1.33 V)
- **Previous 1.15 – 1.35 V was wider than the corner.** The corner is 1.17–1.33 V; widening to ±0.10 V added a generous margin not justified by the chain math.
- **New 1.17 – 1.33 V catches:**
- Stuck FE NMOS OFF (V_pin would read ~2.47 V instead of 1.24 V) — caught (way above 1.33 V)
- Broken FE 2.2 kΩ load resistor (V_pin floats to pullup) — caught
- Pure spec-edge drift — passes correctly
### Nominal-value corrections in YAML inline comment
- Updated the comment from "1.25 V midpoint" / "full 2.5 V" to **"1.24 V"** / **"2.47 V"** with the explanation that the FE VMEAS 200 K divider loads the 2.2 K TA pullup by ~1 %. Future readers won't misinterpret the windows as "centred on 2.5 V".
### Stack assumptions
- **R_DS_on of Q4/Q5 modelled at 10 Ω worst-case at V_GS = 3.3 V (PCA9506 logic).** 2N7002DW datasheet doesn't publish R_DS_on at V_GS = 3.3 V explicitly; conservative estimate based on V_GS = 4.5 V spec (5 Ω typ, 7.5 Ω max) extrapolated to a lower drive voltage. In practice, 10 Ω in series with 2.2 kΩ is < 0.5 % of the divider — negligible compared to the 1 % R tolerance.
- **TA pullup R11..R14 tolerance assumed 1 %.** EGP10000081 (2K2 0402) is the same code as on the FE side; FE is documented as 1 % tolerance in BOM, so TA assumed same.
- **No per-fixture calibration.** Limits derive from worst-case corners. If empirical SPC after ≥10 production runs shows the distribution clustering tightly at ~2.47 V / ~1.24 V with low spread, the windows could be tightened further with confidence.
### What this test does NOT catch
- **GND_SW signal degradation upstream** of Q4/Q5 (e.g., I²C expander U7 partially failing such that GND_SW0..3 toggle slowly or get stuck mid-transition). The test only samples the steady-state V_pin after the runner sets GND_SW. A slow rise on GND_SW that makes the MOSFET partially ON during the sample would produce a reading between 1.24 V and 2.47 V — which would fall outside both windows and fail. Side effect: catches transition issues even without explicitly testing them.
- **Per-channel cross-talk** between J5_FIXED_LOAD channels. Each scenario reads all 4 channels and the runner expects exactly one closed and three open — but the test doesn't explicitly correlate the "other 3 channels stay at 2.47 V" with the active channel's switch state.
## Follow-up actions
1. ~~Update YAML limits~~ — done (20 of 20 windows changed; 16 open + 4 closed).
2. ~~Document derivation~~ — done (this decision).
3. ~~Correct YAML inline comment with actual nominals (~1.24 V, ~2.47 V)~~ — done.
4. **TODO:** After ≥10 production runs, pull SPC stats:
- Open-switch readings should cluster at **2.47 V** (not 2.5 V). Cpk ≥ 1.33 within 2.35–2.61 V.
- Closed-switch readings should cluster at **1.24 V** (not 1.25 V). Cpk ≥ 1.33 within 1.17–1.33 V.
- If distributions are tight, consider per-fixture calibration to tighten windows further.
5. **TODO:** Capture 2N7002DW (EGP10000893) in PLEASE with R_DS_on @ V_GS = 3.3 V curve, so the 10 Ω worst-case assumption is structured rather than estimated.
6. **TODO:** Cross-reference D.08 from any PLEASE test case (PT-SIG-07.*) that maps to a `pt_code` tag in `fe_J5_fixed_load.yaml`. |
|
| 2026-05-26 09:13:46 |
martin.johansson@esharp.se |
update |
decision #19 |
mcp |
show diff
| Field | Before | After |
|---|
| chosenOption | Replace the ad-hoc loopback / fabric windows on `fe_J7_mpio_relay.yaml` with corner-derived limits based on the **AD5593R DAC + ADC** chain (SIG-02 ±0.3 % / ±8 mV per direction) and the **TA patch topology** captured under projectId 14 DUT id=3 (S/N P0).
### Step 1 — FE_MPIO 0..7 loopback (64 measurements)
| Group | Count | Previous YAML | **New YAML** |
|---|---|---|---|
| INIT (idle, expect 0 V) | 8 | −0.01 to +0.01 V | **−0.01 to +0.01 V (kept)** |
| Drive 4 V → partner reads | 8 | 3.98 – 4.02 V | **3.96 – 4.04 V** |
| Drive 0.5 V → partner reads | 8 | 0.49 – 0.51 V | **0.48 – 0.52 V** |
| Crosstalk (other 6 channels while 4 V driven) | 48 | ±0.1 V | **±0.1 V (kept)** |
### Step 2 — FE_MPIO + RELAY fabric (36 measurements)
| Group | Count | Previous YAML | **New YAML** |
|---|---|---|---|
| Rail at pullup (idle + pulled-high in scenarios) | 20 | 2.3 – 2.7 V | **2.40 – 2.62 V** |
| Rail pulled-low (driver active) | 16 | −0.05 to +0.05 V | **−0.05 to +0.05 V (kept)** |
36 limit values changed, 64 kept. | Replace the ad-hoc loopback / fabric windows on `fe_J7_mpio_relay.yaml` with corner-derived limits. The Step 2 (RELAY-fabric) windows are derived from the **full chain through the Sparrow N-Top board** (ESH10000634 R3) which inserts series elements on every J7 line — not just from the TA pullup. The FE-side 1 MΩ MPIO pulldown (SIG-12) loads the rail at idle, shifting V_rail nominal from 2.5 V to ~2.45 V.
### Step 1 — FE_MPIO 0..7 loopback (64 measurements)
| Group | Count | Previous YAML | **New YAML** |
|---|---|---|---|
| INIT (idle, expect 0 V) | 8 | −0.01 to +0.01 V | **−0.01 to +0.01 V (kept)** |
| Drive 4 V → partner reads | 8 | 3.98 – 4.02 V | **3.96 – 4.04 V** |
| Drive 0.5 V → partner reads | 8 | 0.49 – 0.51 V | **0.48 – 0.52 V** |
| Crosstalk (other 6 channels while 4 V driven) | 48 | ±0.1 V | **±0.1 V (kept)** |
Loopback chain (per channel): FE U5 AD5593R → 1 MΩ pulldown (R57/R92/R102/R103/R117/R125/R140/R141) → LSHM J3 → N-Top **39 Ω 1 %** (R3..R17 subset) → **ADG4612** switch (R_DS_on ~1 Ω) → **KGSOT05C** TVS → IDC J7 → TA loopback short → mirror path back. ADC input is HiZ, so DC drops are negligible across the chain elements; the chain doesn't introduce additional gain/offset error at DC.
### Step 2 — FE_MPIO + RELAY fabric (36 measurements) — **corrected**
| Group | Count | Previous YAML | **New YAML** |
|---|---|---|---|
| Rail at pullup (idle + pulled-high in scenarios) | 20 | 2.3 – 2.7 V | **2.34 – 2.56 V** |
| Rail pulled-low (driver active) | 16 | −0.05 to +0.05 V | **−0.01 to +0.05 V** |
20 pullup windows changed (centered on 2.45 V, not 2.5 V). 16 pulled-low windows tightened asymmetrically — physical rail can't go negative, only ADC offset extends below 0.
**Total: 44 of 100 windows changed**, 56 kept. | | rationale | ## Chain topology
### Step 1 — FE_MPIO loopback (channels 0..7)
Per Sparrow FE schematic page 4: **U5 = AD5593R** (EGP10000890, I²C addr 0x11). IO0..IO7 = FE_MPIO_0..FE_MPIO_7. The same chip provides both DAC drive and ADC sense — software configures each channel as ADC or DAC per measurement.
Test adapter shorts paired channels at the J7 IDC pins (0↔2, 1↔3, 4↔6, 5↔7). For each pair:
1. Configure one side as DAC, drive 4.0 V (or 0.5 V).
2. Configure the other side as ADC, read back.
3. While 4.0 V is driven, read the other 6 channels as ADCs (crosstalk check).
### Step 2 — FE_MPIO + RELAY fabric (channels 8..11 + RELAY1..4)
Per Sparrow FE schematic page 4: **U6 = AD5593R** (EGP10000890, I²C addr 0x10). IO0..IO3 = FE_MPIO_8..FE_MPIO_11. (IO4..IO7 carry VIO_SET, VADJ_SET, VMON_VADJ_EXT, VMON_VIO_EXT — used by `fe_J9_pwr.yaml`, unrelated to this test.)
**Fabric topology exists only via TA patches** (DUT-01 / S/N P0, 2026-05-15):
- Rail A: FE_MPIO_8, FE_MPIO_10, RELAY1, RELAY3 tied + 10 kΩ ±5 % pullup to 2.5 V
- Rail B: FE_MPIO_9, FE_MPIO_11, RELAY2, RELAY4 tied + 10 kΩ ±5 % pullup to 2.5 V
Wired-OR semantics: any driver (relay open-drain to GND, or MPIO DAC at 0 V) pulls its rail to 0 V; with all 4 drivers on the rail released, the 10 kΩ pulls the rail to 2.5 V. The patch is documented in projectId 14 DUT notes + notices 22, 23.
The 2.5 V pullup itself is generated by the TA's AMS1117-ADJ (R21 = R22 = 10 kΩ on ADJ) — same source analyzed in D.03 (audio test).
## Tolerance stack
| Source | Tolerance | Reference |
|---|---|---|
| AD5593R DAC gain | ±0.3 % | SIG-02 (chain-level spec) |
| AD5593R DAC offset | ±8 mV | SIG-02 |
| AD5593R ADC gain | ±0.3 % | SIG-02 |
| AD5593R ADC offset | ±8 mV | SIG-02 |
| TA AMS1117 2.5 V rail | +3.5 % / −3.0 % → 2.425–2.588 V | D.03 derivation |
| TA pullup R | 10 kΩ ±5 % | DUT-01 patches #1 + #2 (notices 22, 23) |
| TA loopback short (Step 1) | negligible (HiZ ADC) | TA schematic |
| Wired-OR driver V_OL (relay R_DS_on) | ≈ 0 V (1.4 Ω × 250 µA = 0.35 mV) | KAQY214 / MAX491 family datasheet |
| Wired-OR driver V_OL (MPIO DAC at 0 V) | a few mV at 250 µA sink | AD5593R datasheet |
## Step 1 corner math
**For a DAC→loopback→ADC measurement using the same AD5593R chip**, the DAC and ADC are independent error sources (different IO channels with their own gain/offset paths). The Vref is shared, so Vref drift cancels, but INL and offset don't.
`V_read = V_set × DAC_gain × ADC_gain ± DAC_offset ± ADC_offset`
Treating both directions as ±0.3 % / ±8 mV (SIG-02 published values):
- Combined gain: (1 ± 0.003) × (1 ± 0.003) ≈ 1 ± 0.006 → **±0.6 %**
- Combined offset: ±8 mV + ±8 mV = **±16 mV** worst case (sequential, not RSS)
### Drive 4.0 V
| Corner | V_set | × gain | ± offset | V_read |
|---|---|---|---|---|
| Worst-low | 4.0 V | × 0.994 | − 0.016 | **3.960 V** |
| Nominal | 4.0 V | × 1.000 | 0 | 4.000 V |
| Worst-high | 4.0 V | × 1.006 | + 0.016 | **4.040 V** |
YAML window → **3.96 – 4.04 V**. Previous 3.98–4.02 V was half this corner — a unit at the worst process corner would nuisance-fail.
### Drive 0.5 V
| Corner | V_set | × gain | ± offset | V_read |
|---|---|---|---|---|
| Worst-low | 0.5 V | × 0.994 | − 0.016 | **0.481 V** |
| Worst-high | 0.5 V | × 1.006 | + 0.016 | **0.519 V** |
YAML window → **0.48 – 0.52 V**. Previous 0.49–0.51 V was half the corner.
### INIT (idle, expect 0 V)
The DAC is set to 0 V (or chip output is HiZ + 1 MΩ pulldown → 0 V). The ADC reads with its own offset only (no DAC contribution at 0 V to amplify). Worst-case = ±8 mV (SIG-02 offset). YAML ±0.01 V matches with 2 mV margin. **Kept.**
### Crosstalk (other 6 channels read while 4 V is driven on one channel)
Physical DC crosstalk via ribbon-cable parasitic R is ≪ 1 mV (no shared current path; each channel has its own DAC driving its own pin into a HiZ ADC). The ±0.1 V window allows for:
- AC capacitive coupling during the drive transient (if ADC samples too soon after DAC settles)
- ADC offset (±8 mV)
- A wide margin for fixture variation
DC steady-state crosstalk should be sub-mV. Kept ±0.1 V as a practical capacitive-coupling allowance; tighten in a follow-up if production data shows headroom.
## Step 2 corner math
### Rail at pullup (idle / pulled-high)
`V_read = V_pullup × ADC_gain ± ADC_offset` (single-direction read; no DAC involved when channel is configured as input)
| Corner | V_pullup (TA AMS1117) | × ADC gain | ± offset | V_read |
|---|---|---|---|---|
| Worst-low | 2.425 V (D.03 floor) | × 0.997 | − 0.008 | **2.410 V** |
| Nominal | 2.500 V | × 1.000 | 0 | 2.500 V |
| Worst-high | 2.588 V (D.03 ceiling) | × 1.003 | + 0.008 | **2.604 V** |
YAML window → **2.40 – 2.62 V** (rounded outward). Previous 2.3–2.7 V was wider than the corner — tightening catches small drift (e.g. AMS1117 reference shift due to aging) that the loose window misses.
Note on leakage: with 4 drivers on the rail (2 MPIO HiZ when configured as ADC + 2 relay open-drain OFF), worst-case combined leakage is < 10 µA → voltage drop across 10 kΩ pullup < 100 µV. Negligible.
### Rail pulled-low (driver active)
| Corner | Driver V_OL | + ADC offset | V_read |
|---|---|---|---|
| Worst-low | 0 V (negative excursion impossible — driver pulls to GND only) | − 8 mV | **−0.008 V** |
| Typical | ~ 5 mV (DAC at 0 V sinking 250 µA, or relay R_DS_on drop) | ±8 mV | −3 to +13 mV |
| Worst-high | ~ 50 mV (degraded driver or high-side leakage) | + 8 mV | **+0.058 V** |
YAML window → **−0.05 to +0.05 V** (kept). Within the corner with small margin on the high side.
## Source documents
- Sparrow Hardware Datasheet v3 — SIG-02 (FE_MPIO ±0.3 % gain + ±8 mV offset)
- Sparrow FE PCBA schematic page 4 ("Fixture MPIO & Monitor") — U5/U6 AD5593R + 1 MΩ pulldowns
- AD5593R datasheet (EGP10000890) — 12-bit DAC/ADC, 4 mV V_OL at 250 µA sink
- Sparrow TA schematic — pullup network is **patches** not schematic; see projectId 14 DUT id=3, notices 22 + 23 + 24
- PLEASE D.03 — TA AMS1117 V_pullup tolerance derivation (+3.5 % / −3.0 %)
- PLEASE Q-TA-01 — open question on R48 function | ## Chain topology — Step 2 (RELAY fabric)
The J7 fabric is **not** a simple "10 kΩ to 2.5 V on the TA, MPIO/relay drivers on the FE". It passes through three boards and the components on each affect both the idle voltage and the pulled-low voltage.
### Per-J7-pin chain (from TA back to FE)
```
TA pullup network (patches #1 + #2)
10 kΩ ±5 % → 2.5 V (TA AMS1117, per D.03: 2.425–2.588 V)
│
J7 pin (IDC connector on N-Top, EGP10001499)
│
┌───┴────────────────────────────────────────────────────┐
│ N-Top board (ESH10000634 R3) │
│ │
│ For FE_MPIO_8..11 pins (J7-4, 6, 8, 10): │
│ ──→ ADG4612 switch (R_DS_on ~1 Ω, always ON via │
│ R12/R13 1 kΩ pullup to 5 V on U2/U3 IN) │
│ ──→ 39 Ω 1 % series R (R4/R5/R8/R9) │
│ ──→ TVS KGSOT05C to GND (D31, D32; leakage ~nA) │
│ ──→ LSHM J3 pin (DATA1-56..59) │
│ │
│ For RELAY1..4 pins (J7-12, 14, 16, 18): │
│ ──→ 220 Ω || 220 Ω = 110 Ω (R20||R21 etc.) │
│ ──→ G20N06D52 MOSFET drain (R_DS_on ~mΩ, negligible)│
│ ──→ Source → GND │
│ ──→ Gate driven by FE USR_GPIO1..4 via 3K3 pulldown │
│ (R31..R34, fail-safe gate-low when FE HiZ) │
│ ──→ TVS VGSOT24C on drain (D87, D88; ESD/flyback) │
└─────────────────────────────────────────────────────────┘
│
LSHM J3 pin (data line between FE and N-Top)
│
┌───┴────────────────────────────────────────────────────┐
│ FE board (ESH10000540 R3) │
│ For FE_MPIO_8..11 (J3-7, 8, 11, 12): │
│ ──→ 1 MΩ pulldown to GND (R171..R174, per SIG-12) │
│ ──→ AD5593R U6 (DAC/ADC channel, IO0..IO3) │
│ │
│ For USR_GPIO1..4 (J3-13..16) — the "RELAY drivers": │
│ ──→ from PCA9506 I/O expander U7 (open-drain │
│ outputs to N-Top's MOSFET gates) │
└─────────────────────────────────────────────────────────┘
```
Note: the test's "RELAY1..4" signals are **not** controlled by FE-side 2N7002 MOSFETs — they're driven by **USR_GPIO1..4 (FE I/O expander)** through the LSHM, which then drive the **G20N06D52 MOSFETs on the N-Top board** (Q1, Q2). The MOSFETs' drains pull the J7 fabric rail toward GND through the 110 Ω current-limit network.
### Chain topology — Step 1 (FE_MPIO 0..7 loopback)
Same as Step 2 for the FE_MPIO routing (39 Ω + ADG4612 + TVS through N-Top) except:
- No TA pullup (TA shorts paired channels directly: J7-4↔J7-8, etc.)
- No RELAY drivers in play
- DAC drives one channel, ADC reads the other via the loopback short
At HiZ ADC input current, the 39 Ω + ADG4612 elements introduce sub-mV drops at all test voltages (4 V, 0.5 V, 0 V). So Step 1 windows are dominated by the AD5593R DAC + ADC accuracy, as originally derived.
## Tolerance stack — Step 2
| Source | Tolerance | Reference |
|---|---|---|
| TA pullup R | 10 kΩ ±5 % | TA patches #1 + #2 (notice 22 + 23) |
| V_pullup source (TA AMS1117) | +3.5 % / −3.0 % → 2.425–2.588 V | D.03 |
| FE pulldown (per FE_MPIO line) | 1 MΩ ±1 % | FE BOM R171..R174 EGP10000145 |
| FE pulldown parallel on rail (2 lines per rail) | 500 kΩ ±~1 % (495–505 kΩ) | derived |
| ADG4612 R_DS_on | 1 Ω typ, 1.6 Ω max | EGP10001881 datasheet |
| Series 39 Ω | ±1 % | N-Top BOM EGP10000040 |
| RELAY current-limit (R20\|\|R21 etc.) | 220 \|\| 220 = 110 Ω ±~1 % | N-Top BOM EGP10000493 |
| G20N06D52 R_DS_on | ~few mΩ (negligible at 250 µA) | datasheet |
| G20N06D52 drain leakage (OFF, 85 °C) | up to ~1 µA per channel, ~2 µA per rail | datasheet |
| AD5593R gain + offset | ±0.3 % + ±8 mV (per chain direction) | PLEASE SIG-02 |
## Step 2 corner math — corrected
### Rail at pullup (idle / pulled-high)
Each rail has two MPIO branches, each ending in 1 MΩ to GND on the FE → **500 kΩ parallel pulldown** loads the 10 kΩ TA pullup. The N-Top series chain (39 Ω + 1 Ω ADG4612) is in series with each pulldown but adds negligible drop at the 5 µA idle current per branch.
`V_rail = V_pullup × R_pulldown_par / (R_pulldown_par + R_pullup) − I_MOSFET_leak × R_pullup`
| Corner | V_pullup | R_pullup | R_pulldown_par | I_MOSFET_leak | V_rail (raw) | × ADC + offset | V_read |
|---|---|---|---|---|---|---|---|
| Worst-low (cold rail, high R_pullup, low R_par, max leakage) | 2.425 V | 10.5 kΩ | 495 kΩ | 2 µA @ 85 °C | 2.354 V | × 0.997 − 0.008 | **2.339 V** |
| Nominal (25 °C, typical) | 2.500 V | 10 kΩ | 500 kΩ | ~0 µA | 2.451 V | × 1.000 | 2.451 V |
| Worst-high (hot rail, low R_pullup, high R_par, no leakage) | 2.588 V | 9.5 kΩ | 505 kΩ | 0 µA | 2.540 V | × 1.003 + 0.008 | **2.556 V** |
YAML window → **2.34 – 2.56 V** (rounded outward to 5 mV).
The nominal is **2.451 V**, not 2.5 V — the FE-side 1 MΩ pulldowns load the rail by ~50 mV. **Important for production SPC analysis**: the distribution should centre around 2.45 V, not 2.5 V. Anyone interpreting "rail at pullup = 2.5 V" needs to expect 2.45 V instead.
### Rail pulled-low (driver active)
The N-Top inserts deliberate current-limiting in series with **every** driver path. The driver doesn't pull the rail all the way to GND — it pulls it down through a divider against the 10 kΩ pullup.
| Driver | Series R | V_rail = 2.5 V × R_series / (10 K + R_series) | Plus ADC offset |
|---|---|---|---|
| **MPIO drives 0 V** (DAC + 39 Ω + ADG4612 ≈ 40 Ω) | 40 Ω | **~10 mV** | ±8 mV |
| **RELAY fires** (R20\|\|R21 = 110 Ω + G20N06D52 R_DS_on ~mΩ) | 110 Ω | **~27 mV** | ±8 mV |
| Both an MPIO and a RELAY fire (rare in test) | 40 \|\| 110 ≈ 29 Ω | ~7 mV | ±8 mV |
| Two RELAYs fire (ganged — see DUT-01 patch limitation) | 110 \|\| 110 = 55 Ω | ~14 mV | ±8 mV |
Worst-case readings:
- Worst-low: 0 V (driver can't go negative) − 8 mV (ADC offset) = **−0.008 V**
- Worst-high: 30 mV (relay-side high corner) + 8 mV (ADC offset) = **+0.038 V**
YAML window → **−0.01 to +0.05 V** (rounded outward, slight margin on high side).
The previous symmetric ±0.05 V window allowed up to −50 mV on the low side, which can't physically happen — only the ADC offset can produce negative readings. Tightening the low bound to −0.01 V catches a stuck-high reading earlier without losing any real-fault sensitivity.
## Step 1 corner math — unchanged
DAC+ADC compounded chain, same as original D.07: 4.0 V → 3.96–4.04 V; 0.5 V → 0.48–0.52 V. The N-Top series chain (39 Ω + 1 Ω ADG4612 each direction, ~80 Ω round-trip) doesn't introduce gain/offset error at HiZ ADC current, so the original AD5593R chain math holds.
## Source documents
- Sparrow FE PCBA ESH10000540 R3 — schematic page 4 (U5/U6 AD5593R + R171..R174 pulldowns), schematic page 3 (U7 PCA9506BS I/O expander → USR_GPIO1..4 driving J3-13..16), schematic page 9 (FE J3 LSHM connector)
- Sparrow IDC N-Top PCBA ESH10000634 R3 — schematic + netlist `NetList_Sparrow_FE_N-Top_R3.qcv` (U2/U3/U4 ADG4612, Q1/Q2 G20N06D52, R3..R17 39 Ω, R20..R30 220 Ω, R31..R34 3K3, R12/R13/R19 1 kΩ, D31/D32 KGSOT05C, D87/D88 VGSOT24C)
- Sparrow Test Adapter ESH10000654 R0 — patches #1 + #2 (DUT-01 / S/N P0): 10 kΩ ±5 % pullup to 2.5 V on rail A + B (notices 22 + 23)
- PLEASE D.03 — TA AMS1117 V_pullup tolerance (+3.5 % / −3.0 %)
- PLEASE SIG-02 — FE_MPIO chain accuracy (±0.3 % / ±8 mV per direction)
- PLEASE SIG-12 — MPIO pulldown spec (1 MΩ to GND)
- PLEASE Q-TA-01 — open: R48 function on TA
- AD5593R datasheet (EGP10000890), ADG4612 datasheet (EGP10001881), G20N06D52 datasheet (EGP10001048) | | tradeOffs | ## Tradeoffs accepted
- **Drive 4 V / 0.5 V windows widened from ±0.02 / ±0.01 V to ±0.04 / ±0.02 V.** Previous windows assumed a single-direction chain accuracy (DAC OR ADC, not both). Loopback compounds both, so the corner is ±0.04 V at 4 V and ±0.02 V at 0.5 V. Previous tight windows would nuisance-fail at process+temp corners. The new windows catch:
- Open driver (V_read = 0 V or rail) — easily flagged
- Failed loopback short on TA (V_read = floating, typically rail or driven by leakage) — flagged
- DAC stuck at wrong code — caught if outside the new window
- Pure linearity / offset drift — passes if both chain directions are within SIG-02 spec
- **Fabric pullup window tightened from ±0.2 V to ±0.11 V.** Previous 2.3–2.7 V was wider than the AMS1117 + ADC corner could deliver. Tightening to 2.40–2.62 V matches the corner with the standard 1 mV outward rounding. A unit drifting outside this window indicates real degradation (Vref aging, ADC calibration loss, or a leaky driver pulling the rail mid-way). Risk: a unit running at one of the AMS1117 corners + ADC at the matching corner sits right at the limit edge. Mitigated by the 4 mV margin from the formal corner.
- **Crosstalk window not tightened.** Physically the DC corner is sub-mV (no shared current path between MPIO channels through the ribbon cable), but the ±0.1 V window is a practical allowance for AC capacitive coupling during the drive transient. If the runner samples > 1 ms after drive settles, the AC is fully decayed and the window is overkill — tightening to ±0.02 V would catch some real coupling-induced offsets. Deferred until we know the sample timing in `fe_J7_mpio_relay.py`.
- **INIT window not tightened.** Already at ±0.01 V which matches the SIG-02 offset bound. No reason to change.
- **Pulled-low window unchanged.** The corner is approx −0.01 to +0.06 V; current ±0.05 V is 5 mV tighter on the high side, which catches a slightly-degraded driver (V_OL > 50 mV) that the strict-corner window would miss. Reasonable tradeoff.
- **Test depends on TA patches that are not in the schematic.** Without DUT-01 (S/N P0) patches #1 + #2, the Step 2 fabric does not exist. This is acceptable today because:
- All current Sparrow integration testing uses DUT-01.
- The dependency is now structurally captured in PLEASE (projectId 14 DUT id=3 + notices 22, 23, 24).
- The YAML header now explicitly warns about this.
Risk: if a second TA is built without patches applied, `fe_J7_mpio_relay` Step 2 will silently fail. Mitigation: the next-rev TA design (notice 25) should fold the fabric into the schematic so a clean board passes.
- **R48 function still unknown (Q-TA-01).** R48 was missing on the as-built TA and was patched in (patch #3 / notice 24). If R48 turns out to be required for relay-driver operation, then `fe_J7_mpio_relay` Step 2 has a *third* patch dependency that's not yet documented in the schematic. Q-TA-01 is the action item to resolve this.
- **No per-board calibration.** Limits derive from datasheet worst-case for both U5/U6 AD5593R chips and the AMS1117 on the TA. Per-board calibration could tighten the windows substantially (especially for the fabric pullup, which is one specific TA's AMS1117).
## Follow-up actions
1. ~~Update YAML limits~~ — done (`fe_J7_mpio_relay.yaml`, 36 of 100 windows changed, 64 kept).
2. ~~Document derivation~~ — done (this decision).
3. **TODO (open):** Answer Q-TA-01 — what is R48's net function? If critical for relay-driver operation, this test depends on patch #3 too.
4. **TODO:** Capture U5 and U6 AD5593R chips into PLEASE via `please_component_create` so the SIG-02 ±0.3 % / ±8 mV assumption is structured rather than free-text in this decision.
5. **TODO:** Verify the sample timing in `fe_J7_mpio_relay.py`. If samples are > 1 ms after DAC drives, tighten crosstalk window to ±0.02 V. If samples are < 100 µs, leave ±0.1 V or even consider raising it.
6. **TODO:** After ≥10 production runs through `fe_J7_mpio_relay`, pull SPC stats. Specifically:
- Drive 4 V Cpk — should be ≥ 1.33 with new windows
- Pullup readings Cpk — should be ≥ 1.33; if not, investigate AMS1117 calibration on TA
- Crosstalk distribution — confirm < ±10 mV typical, otherwise revisit ribbon-cable / fixture grounding
7. **TODO:** When the next-rev TA (ESH10000654 R1) lands with the relay-readback fabric in-schematic (per notice 25, option 1 or 3), update this YAML's header to remove the "depends on patches" warning.
8. **TODO:** Cross-reference D.07 from any PLEASE test case (PT-SIG-*) that maps to a `pt_code` tag in `fe_J7_mpio_relay.yaml`. | ## Tradeoffs accepted
### Step 1 — loopback windows widened (unchanged from initial D.07)
- **Drive 4 V / 0.5 V windows widened from ±0.02 / ±0.01 V to ±0.04 / ±0.02 V.** Previous windows assumed a single-direction chain accuracy (DAC OR ADC, not both). Loopback compounds both, so the corner is ±0.04 V at 4 V and ±0.02 V at 0.5 V. New windows match the chain corner without losing fault sensitivity (open driver, broken loopback short, stuck DAC code all still caught).
- **INIT, crosstalk, kept.** INIT at ±0.01 V matches the SIG-02 offset bound. Crosstalk at ±0.1 V is a practical capacitive-coupling allowance during the drive transient (DC corner is sub-mV).
### Step 2 — rail-at-pullup window corrected (this revision)
- **Window shifted DOWN from 2.40–2.62 V to 2.34–2.56 V (centred on 2.45 V, not 2.5 V).** Earlier derivation in D.07 missed the FE-side 1 MΩ pulldowns on each FE_MPIO line. With 2 MPIO lines tied to each rail via TA patches #1 + #2, the parallel pulldown (500 kΩ) loads the 10 kΩ TA pullup and drops V_rail by ~50 mV at idle. The 2.40 V floor in the earlier version would nuisance-fail at worst-corner (cold rail + leakage at 85 °C → 2.339 V at the ADC). The corrected window accommodates the real corner and centres on the physically-expected 2.45 V nominal.
- **Tighter than the previous placeholder ±0.2 V (2.3–2.7 V).** New 2.34–2.56 V window catches small drift (AMS1117 reference shift, ADC calibration loss, leaky driver) that the placeholder window missed.
- **Production SPC implication: the distribution centres on 2.45 V, not 2.5 V.** Anyone reading the YAML number `2.5 V nominal` should expect actual readings at ~2.45 V; only failures below 2.34 V or above 2.56 V are real issues. Cpk analysis should use 2.45 V as the target.
### Step 2 — pulled-low window tightened asymmetric (this revision)
- **Tightened from −0.05/+0.05 V to −0.01/+0.05 V (asymmetric).** The previous symmetric ±0.05 V allowed up to −50 mV on the low side, which is physically impossible (no driver source drives negative; only the ADC offset can produce a negative reading, bounded by ±8 mV per SIG-02). Tightening to −0.01 V (with 2 mV margin past the ADC offset) catches a stuck-high reading earlier.
- **High bound 0.05 V unchanged.** Worst-case is 30 mV (relay-side V_rail = 2.5 V × 110 / 10110) + 8 mV ADC offset = 38 mV. 50 mV ceiling leaves 12 mV margin for component drift.
- **Two distinct expected V_rail values in pulled-low state.** MPIO-driven readings will cluster at ~10 mV; relay-driven readings at ~27 mV. Both pass the −0.01 to +0.05 V window. **Production SPC implication**: a histogram of pulled-low readings should show a bimodal distribution (10 mV peak for MPIO drives, 27 mV peak for relay drives). A unimodal distribution at 10 mV across scenarios where relays SHOULD fire would indicate the MOSFET driver isn't being engaged correctly.
### Test depends on multiple boards' patches/topology
- **TA patches #1 + #2 required** for the Step 2 fabric to exist (see DUT-01 notice 22, 23). On a clean ESH10000654 R0 (no patches), Step 2 readings would float.
- **N-Top board ESH10000634 R3 is on the path with active circuitry.** Steps 1 and 2 both rely on the ADG4612 switches being ON (kept by R12/R13/R19 pullup to 5 V). If 5 V on the N-Top is missing or degraded, the switches go OFF and the whole test loses signal continuity. This is a single point of failure not currently tested in isolation.
- **FE I/O expander U7 must work** for RELAY1..4 to be drivable. USR_GPIO1..4 are open-drain outputs from U7 (PCA9506BS) at I²C address 0x20. Loss of the I/O expander → no relay drive → fabric stuck at pullup. This is checked indirectly (any I²C scan would catch a dead U7), but a dedicated USR_GPIO drive-and-verify step would be more direct.
### Stack assumptions documented for future verification
- **Worst-case stack (not RSS) used.** RSS would give 15–30 % tighter windows but assumes independence of all error sources, which we can't guarantee (resistor lots can skew systematically; thermal correlation across nearby components).
- **MOSFET drain leakage modelled at 2 µA per rail @ 85 °C.** Conservative — could be lower (sub-µA total) at room temp. Will revisit if production data shows headroom on the high side of the pullup window.
- **No per-board calibration.** All limits derive from datasheet worst-case for FE U5/U6 (AD5593R), N-Top U2/U3/U4 (ADG4612), N-Top Q1/Q2 (G20N06D52), and TA U3 (AMS1117). Per-fixture calibration could tighten windows substantially, especially the pulled-low side where the TA-specific 10 kΩ patch resistor dominates.
### Step 1 derivation re-verified through N-Top chain
- **39 Ω + ADG4612 on every FE_MPIO line confirmed for FE_MPIO_0..7 (Step 1) as well as 8..11 (Step 2).** U4 ADG4612 covers FE_MPIO_4..7, U3 covers MPIO_2/3/10/11, U2 covers MPIO_8/9. Loopback test paths therefore each have ~80 Ω round-trip series resistance — negligible at HiZ ADC current. The original AD5593R chain math (D.07 Step 1) is unaffected.
## Follow-up actions
1. ~~Update YAML limits~~ — done (44 of 100 windows changed; 56 kept).
2. ~~Document derivation (corrected for N-Top chain + FE pulldown loading)~~ — done (this decision).
3. ~~Capture N-Top components in PLEASE (ADG4612, G20N06D52, R-chain, TVS diodes)~~ — already in PLEASE Brain (projectId 7) from earlier `_merge_mes_bom.py` ingestion. Same for FE 1 MΩ pulldowns (projectId 5). Enriching descriptions/properties for the relevant components is a separate cleanup task.
4. **TODO (open):** Answer Q-TA-01 — R48 function. Independent of D.07 but blocks "clean Sparrow TA R0 acceptance criteria".
5. **TODO:** After ≥10 production runs through `fe_J7_mpio_relay`, pull SPC stats:
- Pullup readings should cluster around **2.45 V** (NOT 2.5 V). Cpk ≥ 1.33 within 2.34–2.56 V.
- Pulled-low readings should show **bimodal distribution** at ~10 mV (MPIO-driven) and ~27 mV (relay-driven). Confirm both clusters within 0–50 mV.
- Drive 4 V Cpk ≥ 1.33 within 3.96–4.04 V.
6. **TODO:** Verify the sample timing in `fe_J7_mpio_relay.py` (re crosstalk window decision).
7. **TODO:** When the next-rev TA (ESH10000654 R1) lands with the relay-readback fabric in-schematic (per notice 25), update this YAML's header to remove the "depends on patches" warning.
8. **TODO:** Add a dedicated test step that exercises USR_GPIO1..4 directly (drive HIGH and verify the N-Top MOSFET drains pull low). Currently this is checked indirectly via the fabric test.
9. **TODO:** Cross-reference D.07 from any PLEASE test case (PT-SIG-*) that maps to a `pt_code` tag in `fe_J7_mpio_relay.yaml`.
## Change history
- **2026-05-25 (D.07 initial):** Derived windows assuming TA-only pullup chain (missed N-Top series elements + FE pulldown loading). Step 2 pullup window was 2.40–2.62 V; pulled-low ±0.05 V.
- **2026-05-26 (this revision):** Corrected after tracing FE → LSHM → N-Top → IDC J7 chain via Sparrow_FE_N-Top_R3 schematic + netlist. Identified ADG4612 switches, 39 Ω series, 220 Ω/MOSFET relay-driver chain, and the FE-side 1 MΩ pulldowns. Step 2 pullup window shifted to 2.34–2.56 V (centred on 2.45 V); pulled-low tightened asymmetric to −0.01/+0.05 V. |
|
| 2026-05-26 07:50:44 |
martin.johansson@esharp.se |
create |
decision #19 |
mcp |
show diff
| Field | Before | After |
|---|
| chosenOption | — | Replace the ad-hoc loopback / fabric windows on `fe_J7_mpio_relay.yaml` with corner-derived limits based on the **AD5593R DAC + ADC** chain (SIG-02 ±0.3 % / ±8 mV per direction) and the **TA patch topology** captured under projectId 14 DUT id=3 (S/N P0).
### Step 1 — FE_MPIO 0..7 loopback (64 measurements)
| Group | Count | Previous YAML | **New YAML** |
|---|---|---|---|
| INIT (idle, expect 0 V) | 8 | −0.01 to +0.01 V | **−0.01 to +0.01 V (kept)** |
| Drive 4 V → partner reads | 8 | 3.98 – 4.02 V | **3.96 – 4.04 V** |
| Drive 0.5 V → partner reads | 8 | 0.49 – 0.51 V | **0.48 – 0.52 V** |
| Crosstalk (other 6 channels while 4 V driven) | 48 | ±0.1 V | **±0.1 V (kept)** |
### Step 2 — FE_MPIO + RELAY fabric (36 measurements)
| Group | Count | Previous YAML | **New YAML** |
|---|---|---|---|
| Rail at pullup (idle + pulled-high in scenarios) | 20 | 2.3 – 2.7 V | **2.40 – 2.62 V** |
| Rail pulled-low (driver active) | 16 | −0.05 to +0.05 V | **−0.05 to +0.05 V (kept)** |
36 limit values changed, 64 kept. | | code | — | D.07 | | id | — | 19 | | rationale | — | ## Chain topology
### Step 1 — FE_MPIO loopback (channels 0..7)
Per Sparrow FE schematic page 4: **U5 = AD5593R** (EGP10000890, I²C addr 0x11). IO0..IO7 = FE_MPIO_0..FE_MPIO_7. The same chip provides both DAC drive and ADC sense — software configures each channel as ADC or DAC per measurement.
Test adapter shorts paired channels at the J7 IDC pins (0↔2, 1↔3, 4↔6, 5↔7). For each pair:
1. Configure one side as DAC, drive 4.0 V (or 0.5 V).
2. Configure the other side as ADC, read back.
3. While 4.0 V is driven, read the other 6 channels as ADCs (crosstalk check).
### Step 2 — FE_MPIO + RELAY fabric (channels 8..11 + RELAY1..4)
Per Sparrow FE schematic page 4: **U6 = AD5593R** (EGP10000890, I²C addr 0x10). IO0..IO3 = FE_MPIO_8..FE_MPIO_11. (IO4..IO7 carry VIO_SET, VADJ_SET, VMON_VADJ_EXT, VMON_VIO_EXT — used by `fe_J9_pwr.yaml`, unrelated to this test.)
**Fabric topology exists only via TA patches** (DUT-01 / S/N P0, 2026-05-15):
- Rail A: FE_MPIO_8, FE_MPIO_10, RELAY1, RELAY3 tied + 10 kΩ ±5 % pullup to 2.5 V
- Rail B: FE_MPIO_9, FE_MPIO_11, RELAY2, RELAY4 tied + 10 kΩ ±5 % pullup to 2.5 V
Wired-OR semantics: any driver (relay open-drain to GND, or MPIO DAC at 0 V) pulls its rail to 0 V; with all 4 drivers on the rail released, the 10 kΩ pulls the rail to 2.5 V. The patch is documented in projectId 14 DUT notes + notices 22, 23.
The 2.5 V pullup itself is generated by the TA's AMS1117-ADJ (R21 = R22 = 10 kΩ on ADJ) — same source analyzed in D.03 (audio test).
## Tolerance stack
| Source | Tolerance | Reference |
|---|---|---|
| AD5593R DAC gain | ±0.3 % | SIG-02 (chain-level spec) |
| AD5593R DAC offset | ±8 mV | SIG-02 |
| AD5593R ADC gain | ±0.3 % | SIG-02 |
| AD5593R ADC offset | ±8 mV | SIG-02 |
| TA AMS1117 2.5 V rail | +3.5 % / −3.0 % → 2.425–2.588 V | D.03 derivation |
| TA pullup R | 10 kΩ ±5 % | DUT-01 patches #1 + #2 (notices 22, 23) |
| TA loopback short (Step 1) | negligible (HiZ ADC) | TA schematic |
| Wired-OR driver V_OL (relay R_DS_on) | ≈ 0 V (1.4 Ω × 250 µA = 0.35 mV) | KAQY214 / MAX491 family datasheet |
| Wired-OR driver V_OL (MPIO DAC at 0 V) | a few mV at 250 µA sink | AD5593R datasheet |
## Step 1 corner math
**For a DAC→loopback→ADC measurement using the same AD5593R chip**, the DAC and ADC are independent error sources (different IO channels with their own gain/offset paths). The Vref is shared, so Vref drift cancels, but INL and offset don't.
`V_read = V_set × DAC_gain × ADC_gain ± DAC_offset ± ADC_offset`
Treating both directions as ±0.3 % / ±8 mV (SIG-02 published values):
- Combined gain: (1 ± 0.003) × (1 ± 0.003) ≈ 1 ± 0.006 → **±0.6 %**
- Combined offset: ±8 mV + ±8 mV = **±16 mV** worst case (sequential, not RSS)
### Drive 4.0 V
| Corner | V_set | × gain | ± offset | V_read |
|---|---|---|---|---|
| Worst-low | 4.0 V | × 0.994 | − 0.016 | **3.960 V** |
| Nominal | 4.0 V | × 1.000 | 0 | 4.000 V |
| Worst-high | 4.0 V | × 1.006 | + 0.016 | **4.040 V** |
YAML window → **3.96 – 4.04 V**. Previous 3.98–4.02 V was half this corner — a unit at the worst process corner would nuisance-fail.
### Drive 0.5 V
| Corner | V_set | × gain | ± offset | V_read |
|---|---|---|---|---|
| Worst-low | 0.5 V | × 0.994 | − 0.016 | **0.481 V** |
| Worst-high | 0.5 V | × 1.006 | + 0.016 | **0.519 V** |
YAML window → **0.48 – 0.52 V**. Previous 0.49–0.51 V was half the corner.
### INIT (idle, expect 0 V)
The DAC is set to 0 V (or chip output is HiZ + 1 MΩ pulldown → 0 V). The ADC reads with its own offset only (no DAC contribution at 0 V to amplify). Worst-case = ±8 mV (SIG-02 offset). YAML ±0.01 V matches with 2 mV margin. **Kept.**
### Crosstalk (other 6 channels read while 4 V is driven on one channel)
Physical DC crosstalk via ribbon-cable parasitic R is ≪ 1 mV (no shared current path; each channel has its own DAC driving its own pin into a HiZ ADC). The ±0.1 V window allows for:
- AC capacitive coupling during the drive transient (if ADC samples too soon after DAC settles)
- ADC offset (±8 mV)
- A wide margin for fixture variation
DC steady-state crosstalk should be sub-mV. Kept ±0.1 V as a practical capacitive-coupling allowance; tighten in a follow-up if production data shows headroom.
## Step 2 corner math
### Rail at pullup (idle / pulled-high)
`V_read = V_pullup × ADC_gain ± ADC_offset` (single-direction read; no DAC involved when channel is configured as input)
| Corner | V_pullup (TA AMS1117) | × ADC gain | ± offset | V_read |
|---|---|---|---|---|
| Worst-low | 2.425 V (D.03 floor) | × 0.997 | − 0.008 | **2.410 V** |
| Nominal | 2.500 V | × 1.000 | 0 | 2.500 V |
| Worst-high | 2.588 V (D.03 ceiling) | × 1.003 | + 0.008 | **2.604 V** |
YAML window → **2.40 – 2.62 V** (rounded outward). Previous 2.3–2.7 V was wider than the corner — tightening catches small drift (e.g. AMS1117 reference shift due to aging) that the loose window misses.
Note on leakage: with 4 drivers on the rail (2 MPIO HiZ when configured as ADC + 2 relay open-drain OFF), worst-case combined leakage is < 10 µA → voltage drop across 10 kΩ pullup < 100 µV. Negligible.
### Rail pulled-low (driver active)
| Corner | Driver V_OL | + ADC offset | V_read |
|---|---|---|---|
| Worst-low | 0 V (negative excursion impossible — driver pulls to GND only) | − 8 mV | **−0.008 V** |
| Typical | ~ 5 mV (DAC at 0 V sinking 250 µA, or relay R_DS_on drop) | ±8 mV | −3 to +13 mV |
| Worst-high | ~ 50 mV (degraded driver or high-side leakage) | + 8 mV | **+0.058 V** |
YAML window → **−0.05 to +0.05 V** (kept). Within the corner with small margin on the high side.
## Source documents
- Sparrow Hardware Datasheet v3 — SIG-02 (FE_MPIO ±0.3 % gain + ±8 mV offset)
- Sparrow FE PCBA schematic page 4 ("Fixture MPIO & Monitor") — U5/U6 AD5593R + 1 MΩ pulldowns
- AD5593R datasheet (EGP10000890) — 12-bit DAC/ADC, 4 mV V_OL at 250 µA sink
- Sparrow TA schematic — pullup network is **patches** not schematic; see projectId 14 DUT id=3, notices 22 + 23 + 24
- PLEASE D.03 — TA AMS1117 V_pullup tolerance derivation (+3.5 % / −3.0 %)
- PLEASE Q-TA-01 — open question on R48 function | | title | — | fe_J7_mpio_relay.yaml limit derivation — FE_MPIO loopback + RELAY-fabric (via TA patches) | | tradeOffs | — | ## Tradeoffs accepted
- **Drive 4 V / 0.5 V windows widened from ±0.02 / ±0.01 V to ±0.04 / ±0.02 V.** Previous windows assumed a single-direction chain accuracy (DAC OR ADC, not both). Loopback compounds both, so the corner is ±0.04 V at 4 V and ±0.02 V at 0.5 V. Previous tight windows would nuisance-fail at process+temp corners. The new windows catch:
- Open driver (V_read = 0 V or rail) — easily flagged
- Failed loopback short on TA (V_read = floating, typically rail or driven by leakage) — flagged
- DAC stuck at wrong code — caught if outside the new window
- Pure linearity / offset drift — passes if both chain directions are within SIG-02 spec
- **Fabric pullup window tightened from ±0.2 V to ±0.11 V.** Previous 2.3–2.7 V was wider than the AMS1117 + ADC corner could deliver. Tightening to 2.40–2.62 V matches the corner with the standard 1 mV outward rounding. A unit drifting outside this window indicates real degradation (Vref aging, ADC calibration loss, or a leaky driver pulling the rail mid-way). Risk: a unit running at one of the AMS1117 corners + ADC at the matching corner sits right at the limit edge. Mitigated by the 4 mV margin from the formal corner.
- **Crosstalk window not tightened.** Physically the DC corner is sub-mV (no shared current path between MPIO channels through the ribbon cable), but the ±0.1 V window is a practical allowance for AC capacitive coupling during the drive transient. If the runner samples > 1 ms after drive settles, the AC is fully decayed and the window is overkill — tightening to ±0.02 V would catch some real coupling-induced offsets. Deferred until we know the sample timing in `fe_J7_mpio_relay.py`.
- **INIT window not tightened.** Already at ±0.01 V which matches the SIG-02 offset bound. No reason to change.
- **Pulled-low window unchanged.** The corner is approx −0.01 to +0.06 V; current ±0.05 V is 5 mV tighter on the high side, which catches a slightly-degraded driver (V_OL > 50 mV) that the strict-corner window would miss. Reasonable tradeoff.
- **Test depends on TA patches that are not in the schematic.** Without DUT-01 (S/N P0) patches #1 + #2, the Step 2 fabric does not exist. This is acceptable today because:
- All current Sparrow integration testing uses DUT-01.
- The dependency is now structurally captured in PLEASE (projectId 14 DUT id=3 + notices 22, 23, 24).
- The YAML header now explicitly warns about this.
Risk: if a second TA is built without patches applied, `fe_J7_mpio_relay` Step 2 will silently fail. Mitigation: the next-rev TA design (notice 25) should fold the fabric into the schematic so a clean board passes.
- **R48 function still unknown (Q-TA-01).** R48 was missing on the as-built TA and was patched in (patch #3 / notice 24). If R48 turns out to be required for relay-driver operation, then `fe_J7_mpio_relay` Step 2 has a *third* patch dependency that's not yet documented in the schematic. Q-TA-01 is the action item to resolve this.
- **No per-board calibration.** Limits derive from datasheet worst-case for both U5/U6 AD5593R chips and the AMS1117 on the TA. Per-board calibration could tighten the windows substantially (especially for the fabric pullup, which is one specific TA's AMS1117).
## Follow-up actions
1. ~~Update YAML limits~~ — done (`fe_J7_mpio_relay.yaml`, 36 of 100 windows changed, 64 kept).
2. ~~Document derivation~~ — done (this decision).
3. **TODO (open):** Answer Q-TA-01 — what is R48's net function? If critical for relay-driver operation, this test depends on patch #3 too.
4. **TODO:** Capture U5 and U6 AD5593R chips into PLEASE via `please_component_create` so the SIG-02 ±0.3 % / ±8 mV assumption is structured rather than free-text in this decision.
5. **TODO:** Verify the sample timing in `fe_J7_mpio_relay.py`. If samples are > 1 ms after DAC drives, tighten crosstalk window to ±0.02 V. If samples are < 100 µs, leave ±0.1 V or even consider raising it.
6. **TODO:** After ≥10 production runs through `fe_J7_mpio_relay`, pull SPC stats. Specifically:
- Drive 4 V Cpk — should be ≥ 1.33 with new windows
- Pullup readings Cpk — should be ≥ 1.33; if not, investigate AMS1117 calibration on TA
- Crosstalk distribution — confirm < ±10 mV typical, otherwise revisit ribbon-cable / fixture grounding
7. **TODO:** When the next-rev TA (ESH10000654 R1) lands with the relay-readback fabric in-schematic (per notice 25, option 1 or 3), update this YAML's header to remove the "depends on patches" warning.
8. **TODO:** Cross-reference D.07 from any PLEASE test case (PT-SIG-*) that maps to a `pt_code` tag in `fe_J7_mpio_relay.yaml`. |
|
| 2026-05-26 07:11:16 |
martin.johansson@esharp.se |
create |
decision #18 |
mcp |
show diff
| Field | Before | After |
|---|
| chosenOption | — | Replace the placeholder line-level VMEAS windows on `fe_J9_rs485.yaml` with corner-derived limits based on the MAX491ESD+T transceiver datasheet (V_OD over operating temperature at the 120 Ω loopback load) and the COM-08 VMEAS chain accuracy.
| Measurement | EN state | Previous YAML | **New YAML** |
|---|---|---|---|
| `RS485_LINE_EN_TX_VMEAS` | EN=true (driver active, idle MARK) | 2.5–3.0 V | **2.0–3.5 V** |
| `RS485_LINE_EN_RX_VMEAS` | EN=true (RX side via loopback) | 2.5–3.0 V | **2.0–3.5 V** |
| `RS485_LINE_DIS_TX_VMEAS` | EN=false (driver tri-state) | 0.0–0.1 V | **0.00–0.05 V** |
| `RS485_LINE_DIS_RX_VMEAS` | EN=false (RX side, tri-state) | 0.0–0.1 V | **0.00–0.05 V** |
Loopback string-mode measurements (PASS/true) and the per-baud-rate booleans are not changed — they are pass/fail outcomes, not analog windows.
VMEASP / VMEASN single-ended log entries (no gating) are also unchanged. | | code | — | D.06 | | id | — | 18 | | rationale | — | ## Topology (FE side, Sparrow Fixture Electronics PCBA ESH10000540 R3, schematic page 6)
**Transceiver:** MAX491ESD+T (U24, EGP10001593) — full-duplex RS-485/RS-422, VCC = 5 V, not slew-rate-limited, datasheet rate to 2.5 Mbps. Pinout per Maxim datasheet: pin 4 DE (active high), pin 3 R̅E̅ (active low, tied to RS485_EN logic), pin 9 Y (driver+) → RS485_TX+, pin 10 Z (driver-) → RS485_TX-, pin 11 B (receiver-) → RS485_RX-, pin 12 A (receiver+) → RS485_RX+.
**Loopback path:** Sparrow Test Adapter (ESH10000654 R0) shorts `RS485_TX+ ↔ RS485_RX+` and `RS485_TX- ↔ RS485_RX-` on the J9 IDC connector. R64 = 120 Ω across `RS485_RX+ ↔ RS485_RX-` on the FE acts as the bus termination/load when looped back to TX. Effective driver load = 120 Ω.
**No FE-side fail-safe bias network.** Verified by netlist inspection: no `Vcc → Rb → A` / `B → Rb → GND` resistor pair anywhere near U24. When EN=false, the line floats via the diff-amp resistor network (168 K total) to the ADC inputs (HiZ).
**VMEAS chain (per schematic + netlist trace):**
```
RS485_TX+ ── R208 (140K) ── A ── R240 (14K) ── B ── R207 (14K) ── RS485_TX-
│ │
R245 (120Ω LP) R246 (120Ω LP)
│ │
U40 CH0 U40 CH1 (ADS7828EB, single-ended to GND)
```
RX side mirrors TX: R206 (140K), R239 (14K), R205 (14K), R247/R248 (120 Ω LP), U40 CH2/CH3.
All chain resistors are **1 % tolerance** (EGP10001834 for 14K, EGP10001584 for 140K, EGP10000052 for 120Ω). ADC is **ADS7828EB** (EGP10000946), same part as on the rail VMEAS chains.
Schematic annotation (page 6, near the ADC block):
`Vout = (V+ − V-) × R2 / (R1 + R2 + R3) = (V+ − V-) / 12`
DC analysis (ADC inputs HiZ):
```
i = (V_TX+ − V_TX-) / (R208 + R240 + R207) = (V_TX+ − V_TX-) / 168K
V_node_A = V_TX+ × 28/168 + V_TX- × 140/168
V_node_B = V_TX+ × 14/168 + V_TX- × 154/168
V_node_A − V_node_B = (V_TX+ − V_TX-) × 14/168 = (V_TX+ − V_TX-) / 12 ✓
```
So `V_diff_reported = (V_A_adc − V_B_adc) × 12 = V_OD` (line-level differential).
## Tolerance stack
| Source | Tolerance | Reference |
|---|---|---|
| MAX491 V_OD @ R_L = 54 Ω, 25 °C, V_CC = 5 V | min 1.5 V, typ 2.5 V | Maxim MAX491 datasheet |
| MAX491 V_OD @ 120 Ω load (loopback through R64), over -40°C to +85°C | **2.0 – 4.0 V** | Datasheet curves extrapolated for lighter load |
| FE fail-safe bias network | **none** | Schematic inspection — line floats when EN=false |
| Chain resistors R208/R207/R240 (and RX mirror) | ±1 % | FE BOM |
| ADC ADS7828EB gain | ±0.5 % | EGP10000946 datasheet |
| ADC ADS7828EB offset | ±5 mV | EGP10000946 datasheet |
| VMEAS chain published accuracy (COM-08) | gain ±1.6 %, offset ±6 mV | PLEASE COM-08 |
For the EN=true window we use the COM-08 published chain accuracy (which envelopes the underlying resistor + ADC contributions and is the spec the FE was designed against).
## Corner math — EN=true
`V_reported = V_OD × (1 ± 0.016) ± 0.006 V`
| Corner | V_OD | × gain | ± offset | V_reported |
|---|---|---|---|---|
| Worst-low (driver at low corner of operating-temp envelope) | 2.0 V | × 0.984 | − 0.006 | **1.962 V** |
| Typical (25°C, VCC = 5 V) | ~3.0 V | × 1.000 | 0 | 3.0 V |
| Worst-high (driver at upper corner) | 4.0 V | × 1.016 | + 0.006 | **4.070 V** |
YAML window (rounded outward to 0.1 V) → **2.0 – 3.5 V**.
Note: the **upper** bound was deliberately rounded **inward** to 3.5 V (vs. 4.07 V worst-high). Reason: a V_OD reading > 3.5 V at 120 Ω load on a MAX491 powered from 5 V is unusual — it suggests near-no-load conditions (broken R64 termination on RX side, broken loopback short on TA, or VMEAS chain calibration drift). Catching that is worth the slight reduction from the spec ceiling. If production data shows occasional readings between 3.5 V and 4.0 V on healthy units, widen the upper bound.
## Corner math — EN=false
Driver tri-state. No FE-side fail-safe bias network (confirmed by schematic inspection). Line floats via the 168 K diff-amp network to ADC inputs (HiZ).
| Source | Contribution |
|---|---|
| Driver Hi-Z residual (leakage from MAX491 driver outputs) | < ±5 mV |
| Bias-network common-mode imbalance | 0 (no bias network) |
| Diff-amp R-network DC drift toward 0 V | converges to 0 V (no DC source) |
| VMEAS chain offset (COM-08) | ±6 mV |
| Worst-case sum (RSS) | ~ ±10 mV |
YAML window → **0.00 – 0.05 V** (allows ~5× the worst-case RSS for safety margin while catching any genuine line stuck-state or driver short).
The previous 0.0–0.1 V is wider than needed; tightening to 0.05 V catches a stuck driver (V_OD = 0.05–0.1 V) that the looser window misses.
## Source documents
- MAX491ESD+T (EGP10001593) — Maxim Integrated MAX491 datasheet (full-duplex RS-485/RS-422 transceiver, VCC = 5 V, V_OD @ 54Ω spec 1.5 V min / 2.5 V typ)
- ADS7828EB (EGP10000946) — TI ADS7828 datasheet (12-bit ADC, ±0.5 % gain, ±2 LSB offset at 2.5 V Vref)
- Sparrow Fixture Electronics PCBA ESH10000540 R3 — schematic page 6 ("Fixed Load. UART-RS485.") and netlist (`NetList_Sparrow_FE_R3.qcv`)
- Sparrow Test Adapter ESH10000654 R0 — TX↔RX loopback short
- PLEASE COM-05, COM-08, COM-09 — RS485 functional requirements + VMEAS chain accuracy (gain ±1.6 %, offset ±6 mV) | | title | — | fe_J9_rs485.yaml limit derivation — VMEAS windows from MAX491 V_OD + COM-08 chain accuracy | | tradeOffs | — | ## Tradeoffs accepted
- **EN=true window widened from 2.5–3.0 V to 2.0–3.5 V.** Previous 0.5 V window was tighter than MAX491 V_OD variation over -40°C to +85°C at the 120 Ω loopback load — a unit at V_OD = 2.3 V (well within MAX491 spec) would nuisance-fail the 2.5 V floor; a unit at V_OD = 3.2 V would nuisance-fail the 3.0 V ceiling. New 2.0–3.5 V window catches a degraded driver (V_OD < 2.0 V indicates driver impedance ≫ datasheet typical) while tolerating in-spec variation.
- **EN=true window tighter than COM-08 spec-floor (1.5–5.0 V).** Pure spec-floor would also be valid but would only catch "VDIFF outside the requirement" — i.e., catastrophic failure. The chosen 2.0–3.5 V window catches degradation that's still technically in-spec but indicates trouble. Acceptable tradeoff: spec-compliant units are not penalized (V_OD < 2.0 V at 120 Ω load is below MAX491 typical even at temperature extremes), but degraded units are flagged before they cause field problems.
- **EN=true upper bound rounded inward (3.5 V vs. corner 4.07 V).** A reading > 3.5 V at 120 Ω load is unusual for a healthy unit — V_OD > 4.0 V would imply near-no-load conditions (broken termination R64, broken TA loopback short, or VMEAS calibration drift). Flagging it catches real test-rig integrity faults. Risk: a healthy unit at the upper temp/process corner could land at 3.55 V and nuisance-fail. Will revisit if production data shows this.
- **EN=false window tightened from 0.0–0.1 V to 0.00–0.05 V.** Previous window allowed up to 100 mV residual — physically the line should be very close to 0 V (no driver, no fail-safe bias). 50 mV ceiling catches a stuck or partially-driven output while tolerating chain offset (±6 mV) and worst-case residual leakage. If production shows nuisance-fails, widen back to 0.1 V or implement a signed window (-0.03 to +0.03 V).
- **Low-bound at 0.00 V not negative.** Assumes the software reports |V_diff| (absolute value) or clamps negative readings. If the actual report is signed and the line drifts slightly negative (V_TX- > V_TX+ from imbalance), this window would fail. If empirical data shows negative readings, change to e.g. -0.03 to +0.05 V.
- **No FE-side fail-safe bias confirmed by schematic + netlist inspection.** This is unusual for an RS-485 design (most boards add `Vcc → 680 Ω → A` and `B → 680 Ω → GND` for fail-safe MARK in tri-state). Sparrow FE relies on the loopback test running in EN=true mode for receiver fail-safe validation — but in a non-loopback deployment, the line might not assert MARK reliably when no driver is active. Flagged as a possible future design improvement, not a test issue. Documented in COM-09 acceptance (which mentions "receiver fail-safe bias" — verify the MAX491's internal fail-safe receiver works correctly at the floating bus voltages we see in EN=false).
- **Loopback string-mode results (PASS / true) untouched.** These are pass/fail outcomes from the loopback runner — not derived analog windows. They catch any byte corruption at any baud rate; correct as-is.
- **Conservative outward rounding on EN=true low (2.0 V vs. corner 1.962 V).** Round outward to give 38 mV margin. Catches the same failure modes as 1.96 V but gives more room for chain variation.
## Follow-up actions
1. ~~Update YAML limits~~ — done (`fe_J9_rs485.yaml` v1.0.0, 4 line-level windows updated, derivation header added).
2. ~~Document derivation~~ — done (this decision).
3. **TODO:** After ≥10 production runs through `fe_J9_rs485`, pull SPC stats on `RS485_LINE_EN_TX_VMEAS` and `RS485_LINE_EN_RX_VMEAS`. Confirm:
- All units land within 2.0–3.5 V (otherwise widen)
- Distribution is symmetric / Gaussian around ~3.0 V (otherwise investigate)
- No systematic bias TX vs RX (otherwise investigate VMEAS chain calibration)
4. **TODO:** Capture the MAX491ESD+T (EGP10001593) into PLEASE via `please_component_create` with V_OD spec, so the assumption is structured rather than free-text here.
5. **TODO:** Capture the FE diff-amp resistor chain (R208/R207/R240/R245/R246 and RX mirror) into PLEASE — same as D.04/D.05 follow-up #3.
6. **TODO:** Cross-reference D.06 from any PLEASE test case (PT-COM-*) that maps to a `pt_code` tag in `fe_J9_rs485.yaml` once a coverage matrix is built.
7. **TODO (design-level note for next revision):** Consider adding an external RS-485 fail-safe bias network on the FE (`Vcc → 680 Ω → RS485_RX+`; `RS485_RX- → 680 Ω → GND`). The MAX491 has internal fail-safe but it relies on a specific input voltage. With no external bias, the floating line in EN=false depends on leakage and the diff-amp network. Not a test issue today (test is loopback) but matters in production deployment. |
|
| 2026-05-25 15:25:23 |
martin.johansson@esharp.se |
create |
decision #17 |
mcp |
show diff
| Field | Before | After |
|---|
| chosenOption | — | Replace the placeholder ±3 % (and ±5 % for 12V_EXT_DIV) ON-state windows on `fe_J9_pwr.yaml` with chain-specific corner-derived limits.
**Two distinct measurement chains** per rail get **separate** windows:
- `*_ON_VMON` reads through the **FE-side** ADC (ADS7828EB or AD5593R)
- `*_ON_HOST_V*` reads through the **AccordionQ2 host MPIO** (via the Sparrow Test Adapter)
This catches drift in either chain independently (cross-check).
### VMON windows (FE chain)
| Rail | FE-side chain | Previous YAML | **New YAML** |
|---|---|---|---|
| 1V8_EXT | direct → ADS7828 | 1.746–1.854 V | **1.746–1.834 V** |
| 3V3_EXT | 1 K + 1 K → ADS7828 | 3.201–3.399 V | **3.172–3.431 V** |
| 12V_EXT | 4K3 + 1 K → ADS7828 | 11.40–12.60 V | **11.32–12.70 V** |
| VIO @ 1.5 V | direct → AD5593R | 1.455–1.545 V | **1.464–1.537 V** |
| VIO @ 1.8 V | direct → AD5593R | 1.746–1.854 V | **1.757–1.843 V** |
| VIO @ 2.5 V | direct → AD5593R | 2.425–2.575 V | **2.443–2.558 V** |
| VIO @ 3.3 V | direct → AD5593R | 3.201–3.399 V | **3.226–3.375 V** |
| VADJ @ 1.5 V | 1 K + 1 K → AD5593R | 1.455–1.545 V | **1.444–1.557 V** |
| VADJ @ 1.8 V | 1 K + 1 K → AD5593R | 1.746–1.854 V | **1.735–1.866 V** |
| VADJ @ 2.5 V | 1 K + 1 K → AD5593R | 2.425–2.575 V | **2.413–2.588 V** |
| VADJ @ 3.3 V | 1 K + 1 K → AD5593R | 3.201–3.399 V | **3.189–3.413 V** |
| VADJ @ 4.8 V | 1 K + 1 K → AD5593R | 4.656–4.944 V | **4.643–4.960 V** |
### HOST_V windows (MPIO chain)
| Rail | Host chain | Previous YAML | **New YAML** |
|---|---|---|---|
| 1V8_EXT | TA direct → MPIO | 1.746–1.854 V | **1.747–1.833 V** |
| 3V3_EXT | TA direct → MPIO | 3.201–3.399 V | **3.212–3.388 V** |
| 12V_EXT_DIV | TA 1 K + 124 Ω → MPIO | 1.254–1.386 V | **1.245–1.405 V** |
| VIO @ 1.5 V (pins 7 & 8) | TA direct → MPIO | 1.455–1.545 V | **1.464–1.537 V** |
| VIO @ 1.8 V (pins 7 & 8) | TA direct → MPIO | 1.746–1.854 V | **1.758–1.842 V** |
| VIO @ 2.5 V (pins 7 & 8) | TA direct → MPIO | 2.425–2.575 V | **2.445–2.556 V** |
| VIO @ 3.3 V (pins 7 & 8) | TA direct → MPIO | 3.201–3.399 V | **3.230–3.371 V** |
| VADJ @ 1.5 V | TA direct → MPIO | 1.455–1.545 V | **1.464–1.537 V** |
| VADJ @ 1.8 V | TA direct → MPIO | 1.746–1.854 V | **1.758–1.842 V** |
| VADJ @ 2.5 V | TA direct → MPIO | 2.425–2.575 V | **2.445–2.556 V** |
| VADJ @ 3.3 V | TA direct → MPIO | 3.201–3.399 V | **3.230–3.371 V** |
| VADJ @ 4.8 V | TA direct → MPIO | 4.656–4.944 V | **4.701–4.899 V** |
### Not changed
- **PG / FAULTn booleans** — digital state, no analog window.
- **ON_IMON** ceilings (5–25 mA range) — practical idle-current thresholds for catching leakage / unintended load.
- **PRE_VMON, POST_VMON, PRE_IMON, POST_IMON** — practical "rail off / bleed-out" thresholds. The 12V_EXT POST_VMON's wider window (0.0–0.8 V) tolerates PWR-27's bleed-out τ ≤ 1 s. | | code | — | D.05 | | id | — | 17 | | rationale | — | ## Tolerance stack
| Source | Tolerance | Reference |
|---|---|---|
| 1V8_EXT | 1.76–1.82 V (±1.7 %, asymmetric) | PLEASE PWR-05 |
| 3V3_EXT | 3.23–3.37 V (±2.1 %) | PLEASE PWR-04 |
| 12V_EXT | 11.6–12.4 V (±3.3 %) | PLEASE PWR-03 |
| EXT_VIO | ±1.6 % of set | PLEASE PWR-07 |
| EXT_VADJ | ±1.6 % of set | PLEASE PWR-06 |
| FE divider R's (1 K, 4K3, 1 K, 1 K) | ±1 % | FE BOM |
| TA 12V divider (R51 = 1 K, R52 = 124 Ω) | ±1 % | TA BOM |
| ADS7828EB gain + offset | ±0.5 % + ±5 mV | EGP10000946 datasheet (initial + Vref drift + aging) |
| AD5593R gain + offset | ±0.5 % + ±5 mV | EGP10000890 datasheet (initial + Vref drift + aging) |
| MPIO gain + offset | ±0.3 % + ±8 mV | PLEASE SIG-01 |
## Worst-case math (representative samples — same pattern applies to every rail)
### 1V8_EXT VMON (direct → ADS7828)
`V_mon = V_rail × ADC_gain ± ADC_offset`
| Corner | V_rail | × ADC gain | ± ADC offset | V_mon |
|---|---|---|---|---|
| Worst-low | 1.76 V (PWR-05 floor) | × 0.995 | − 0.005 | **1.746 V** |
| Nominal | 1.80 V | × 1.000 | 0 | 1.800 V |
| Worst-high | 1.82 V (PWR-05 ceiling) | × 1.005 | + 0.005 | **1.834 V** |
YAML window → **1.746–1.834 V**.
### 3V3_EXT VMON (1 K + 1 K → ADS7828)
`V_mon_reported = V_adc_read / nominal_ratio` where `V_adc_read = V_rail × actual_ratio × ADC_gain ± ADC_offset`
Actual ratio with ±1 % R's: low = 990 / (1010+990) = 0.495; high = 1010 / (990+1010) = 0.505. Nominal = 0.500.
| Corner | V_rail | actual_ratio | V_adc | × ADC | V_mon (× 1/0.5) |
|---|---|---|---|---|---|
| Worst-low | 3.23 V | 0.495 | 1.599 V | × 0.995 − 0.005 = 1.586 V | **3.172 V** |
| Worst-high | 3.37 V | 0.505 | 1.702 V | × 1.005 + 0.005 = 1.715 V | **3.431 V** |
YAML window → **3.172–3.431 V**.
### 12V_EXT VMON (4K3 + 1 K → ADS7828)
Actual ratio: low = 990/(4343+990) = 0.18564; high = 1010/(4257+1010) = 0.19177. Nominal = 1/5.3 = 0.18868.
| Corner | V_rail | actual_ratio | V_adc | × ADC | V_mon (× 1/0.18868) |
|---|---|---|---|---|---|
| Worst-low | 11.6 V | 0.18564 | 2.153 V | × 0.995 − 0.005 = 2.138 V | **11.32 V** |
| Worst-high | 12.4 V | 0.19177 | 2.378 V | × 1.005 + 0.005 = 2.395 V | **12.70 V** |
YAML window → **11.32–12.70 V**.
### 12V_EXT HOST_V_DIV (TA 1 K + 124 Ω → MPIO)
Actual ratio: low = 122.76/(1010+122.76) = 0.10838; high = 125.24/(990+125.24) = 0.11230. Nominal = 124/1124 = 0.11032.
| Corner | V_rail | actual_ratio | V_mid | × MPIO | YAML |
|---|---|---|---|---|---|
| Worst-low | 11.6 V | 0.10838 | 1.257 V | × 0.997 − 0.008 = **1.245 V** | |
| Worst-high | 12.4 V | 0.11230 | 1.393 V | × 1.003 + 0.008 = **1.405 V** | |
YAML window → **1.245–1.405 V** (rounded outward).
### VIO @ 2.5 V VMON (direct → AD5593R) — representative for direct-to-AD5593R group
| Corner | V_rail (±1.6 % of 2.5) | × AD5593R | V_mon |
|---|---|---|---|
| Worst-low | 2.460 V | × 0.995 − 0.005 = **2.443 V** | |
| Worst-high | 2.540 V | × 1.005 + 0.005 = **2.558 V** | |
YAML window → **2.443–2.558 V**.
### VADJ @ 2.5 V VMON (1 K + 1 K → AD5593R) — representative for divided-to-AD5593R group
| Corner | V_rail (±1.6 % of 2.5) | actual_ratio | V_adc | × AD5593R | V_mon (× 1/0.5) |
|---|---|---|---|---|---|
| Worst-low | 2.460 V | 0.495 | 1.218 V | × 0.995 − 0.005 = 1.207 V | **2.413 V** |
| Worst-high | 2.540 V | 0.505 | 1.283 V | × 1.005 + 0.005 = 1.294 V | **2.588 V** |
YAML window → **2.413–2.588 V**.
### MPIO chain (HOST_V) — representative VIO @ 2.5 V
| Corner | V_rail | × MPIO | YAML |
|---|---|---|---|
| Worst-low | 2.460 V | × 0.997 − 0.008 = **2.445 V** | |
| Worst-high | 2.540 V | × 1.003 + 0.008 = **2.556 V** | |
YAML window → **2.445–2.556 V**.
## Source documents
- Sparrow Hardware Datasheet v3 §6.2 — external rail specs (PWR-03..07)
- Sparrow Hardware Datasheet v3 §6.11 — VMEAS / IMEAS chain accuracy (PWR-10, PWR-11)
- Sparrow Fixture Electronics PCBA ESH10000540 R3 — FE-side ADC + divider chain (ADS7828EB EGP10000946, AD5593R EGP10000890)
- Sparrow Test Adapter ESH10000654 R0 — TA-side 12V divider (R51 = 1 K, R52 = 124 Ω)
- PLEASE SIG-01 — host MPIO accuracy | | title | — | fe_J9_pwr.yaml limit derivation — VMON / HOST_V windows from rail spec, ADC chain (ADS7828/AD5593R) and MPIO chain | | tradeOffs | — | ## Tradeoffs accepted
- **Chain-specific windows (not unified).** Each rail has separate VMON and HOST_V windows derived from its own measurement chain. For most rails the two windows differ noticeably (e.g. 3V3_EXT: VMON 3.172–3.431 V vs HOST_V 3.212–3.388 V — HOST_V tighter because MPIO is more accurate than the FE ADC chain). For VIO setpoints the windows happen to coincide because AD5593R and MPIO have similar accuracy budgets. Maintenance cost: ~28 distinct limit pairs in the YAML, but each window correctly reflects what its chain can produce — better cross-check and better Cpk in production.
- **Asymmetric rail-spec handling kept literal.** PWR-04 (3.23–3.37 V) and PWR-05 (1.76–1.82 V) are asymmetric around their nominal. The new windows preserve that asymmetry rather than smoothing to ±N%, so a unit at the spec edge can still pass.
- **VMON windows for 1V8_EXT, VIO @ 1V5, VIO @ 1V8, VIO @ 2V5, VIO @ 3V3 are TIGHTER than the previous ±3 % placeholder.** Previous windows were not derived; new windows reflect the actual chain capability. A unit measuring outside the new (tighter) window now indicates a real fault (drift, calibration loss, or rail issue) rather than a placeholder margin.
- **VMON windows for 3V3, 12V, VADJ (all setpoints) are SLIGHTLY WIDER than the previous ±3 %.** The earlier ±3 % could nuisance-fail a unit at the spec edge whose ADC chain corner happened to push the reading outside ±3 %. New windows give correct headroom without losing real fault detection (a 3V3 rail at 3.10 V would still fail the new 3.172 V floor).
- **ADC accuracy estimated at ±0.5 % gain + ±5 mV offset (conservative).** ADS7828EB and AD5593R both have:
- Initial typical: ±0.05 % gain, ±0.1–0.2 % Vref → ~ ±0.2 % gain total
- Vref temp drift: ±10 mV (~ ±0.4 %)
- Long-term aging: ~ ±0.05 %/year × 5 years = ±0.25 %
- INL + offset: ~ ±2 LSB ≈ ±1.2 mV at 2.5 V Vref
- Combined: ~ ±0.5 % + ±5 mV is conservative for steady-state production with environmental swing. Tighter limits possible after per-fixture calibration.
- **No per-fixture calibration captured.** All limits derive from datasheet worst-case for both the FE and TA boards. A future calibration pass could tighten the windows per fixture (especially for the 12V_EXT_DIV which has a 1 K + 124 Ω TA divider that varies fixture-to-fixture).
- **PRE/POST/IMON limits unchanged.** These were not derived from spec in the first place — they're practical thresholds set during early bring-up. Will revisit in a follow-up if production data shows nuisance-fails or systematic drift.
- **12V_EXT_DIV YAML comment updated.** Previous comment said "12 / 9.09 = 1.32 V nominal, ±5 %"; new comment reflects the actual TA topology (R51 = 1 K + R52 = 124 Ω → 1.323 V) and the corner-derived window (1.245–1.405 V).
## Follow-up actions
1. ~~Update YAML limits~~ — done (`fe_J9_pwr.yaml` v1.0.0, 28 ON-state windows + header rewritten).
2. ~~Document derivation~~ — done (this decision).
3. **TODO:** Capture the FE-side ADC chain (ADS7828EB + dividers) into PLEASE as `please_component_create` entries with `sourceRef` pointing at the Sparrow FE schematic, so the ±1 % R / ±0.5 % ADC assumptions are structured rather than free-text in this decision.
4. **TODO:** Capture the TA 12V_EXT_DIV divider (R51 = 1 K, R52 = 124 Ω) into PLEASE — same as D.04 follow-up #3.
5. **TODO:** After ≥10 production runs through `fe_J9_pwr`, pull SPC stats on every ON_VMON and ON_HOST_V measurement; verify Cpk ≥ 1.33. Identify any measurement where the rail is consistently biased to one side of the window — likely indicates a systematic divider or ADC offset that could be calibrated out.
6. **TODO:** Cross-reference D.05 from any PLEASE test cases that get created for `pt_code` tags in `fe_J9_pwr.yaml` once a coverage matrix is built. |
|
| 2026-05-25 15:01:34 |
martin.johansson@esharp.se |
create |
decision #16 |
mcp |
show diff
| Field | Before | After |
|---|
| chosenOption | — | Replace placeholder YAML limits on `fe_Jx_pwr.yaml` with corner-derived windows based on Sparrow Test Adapter (ESH10000654 R0) divider topology + 1% resistors + AccordionQ2 MPIO accuracy (SIG-01):
| Group | Pins | Previous YAML | **New YAML** | Nominal |
|---|---|---|---|---|
| 5V_DIV (J4..J9 mid-points) | 6 | 2.40–2.60 V | **2.33–2.67 V** | 2.500 V |
| 12V_DIV (J4..J9 mid-points) | 6 | 1.00–1.40 V | **1.00–1.18 V** | 1.091 V |
| GND (J4..J9 connector GND pins, excl. J6 AUDIO_GND) | 16 | 0.00–0.20 V | **0.00–0.10 V** | 0 V |
Also corrected the inline comment "12V_DIV → 1.2 V ± 0.2" to "1.09 V nominal, 1.00–1.18 V" — the previous "1.2 V" centre was wrong; nominal mid-point at 12 V rail is 1.091 V (12 × 10K / 110K). | | code | — | D.04 | | id | — | 16 | | rationale | — | ## Test Adapter divider topology (confirmed 2026-05-25)
Per Sparrow_TA_R0 schematic (ESH10000654 R0, sourceRef: ESH10000654/R0/02_Implementation/DesignFiles/Sparrow_TA_R0.pdf):
| Net | Divider | Ratio | Nominal V_mid @ rail nominal |
|---|---|---|---|
| 5V_DIV | 5V → 100K → mid → 100K → GND | 1:2 | 5.0 × 100/200 = **2.500 V** |
| 12V_DIV | 12V → 100K → mid → 10K → GND | 1:11 | 12.0 × 10/110 = **1.091 V** |
Both divider pairs use **1% tolerance** resistors (EGP10000121 = 100K, EGP10000097 = 10K).
## Tolerance stack
| Source | Nominal | Tolerance | Reference |
|---|---|---|---|
| V_5V | 5.0 V | 4.75–5.25 V (±5%) | PLEASE PWR-02 |
| V_12V | 12.0 V | 11.4–12.6 V (±5%) | PLEASE PWR-01 |
| R_top, R_bot | 100K / 10K | ±1% | TA BOM (R1, R3, R4, R7, R9, R10, R15, R16, R17, R18, R19, R20, R29, R30, R41, R42, R43, R44...) |
| MPIO gain | — | ±0.3% | PLEASE SIG-01 |
| MPIO offset | — | ±8 mV | PLEASE SIG-01 |
| GND PTC current | — | Itot ≤ 1.5 A | PLEASE PWR-25 |
## 5V_DIV corner math
V_mid = V_5V × R_bot / (R_top + R_bot)
| Corner | V_5V | R_top | R_bot | V_mid (raw) | + MPIO (×0.997 / ×1.003, ±8 mV) |
|---|---|---|---|---|---|
| Worst-low | 4.75 V | 101K | 99K | 4.75 × 99/200 = 2.351 V | × 0.997 − 0.008 = **2.336 V** |
| Nominal | 5.00 V | 100K | 100K | 2.500 V | 2.500 V |
| Worst-high | 5.25 V | 99K | 101K | 5.25 × 101/200 = 2.651 V | × 1.003 + 0.008 = **2.667 V** |
**YAML window = 2.33–2.67 V** (rounded outward).
## 12V_DIV corner math
V_mid = V_12V × R_bot / (R_top + R_bot)
| Corner | V_12V | R_top | R_bot | V_mid (raw) | + MPIO (×0.997 / ×1.003, ±8 mV) |
|---|---|---|---|---|---|
| Worst-low | 11.4 V | 101K | 9.9K | 11.4 × 9.9/110.9 = 1.018 V | × 0.997 − 0.008 = **1.007 V** |
| Nominal | 12.0 V | 100K | 10K | 1.091 V | 1.091 V |
| Worst-high | 12.6 V | 99K | 10.1K | 12.6 × 10.1/109.1 = 1.166 V | × 1.003 + 0.008 = **1.178 V** |
**YAML window = 1.00–1.18 V** (rounded outward).
## GND corner math
Expected V = 0 V (connector GND tied to system GND through ribbon-cable return).
Contributing terms:
- **GND return IR drop**: PWR-25 caps total rail current at 1.5 A through the PTC. PCB+ribbon-cable GND impedance ≤ 50 mΩ → worst-case 75 mV drop.
- **MPIO offset**: ±8 mV (SIG-01).
Worst-case total ≈ 75 + 8 = 83 mV.
**Production-safe YAML window = 0.00–0.10 V** — leaves a small margin above the physical worst case while still catching any gross GND-integrity fault (broken connector tab, oxidation, unmated pin, missing ribbon-cable return).
## Source documents
- Sparrow Hardware Datasheet v3 §6.1–6.2 — common rail specs (PWR-01, PWR-02, PWR-25)
- Sparrow_TA_R0 schematic — divider topology and resistor BOM
- PLEASE PWR-01, PWR-02, PWR-25, SIG-01 — sourceRef = ESH10000633/R1/01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf | | title | — | fe_Jx_pwr.yaml limit derivation — 5V_DIV / 12V_DIV / GND from divider tolerance stack | | tradeOffs | — | ## Tradeoffs accepted
- **5V_DIV window widened from ±100 mV to ±170 mV.** Previous window (2.40–2.60 V) was tighter than the rail-spec + resistor-tolerance + MPIO-accuracy corner could deliver — at 4.75 V rail + worst resistor corners + MPIO gain/offset corner, a healthy unit could land at 2.336 V and fail. The widened window matches the design's actual capability without losing detection of real rail failures (a rail down to ~4.0 V would still read ~2.0 V and fail the low limit).
- **12V_DIV window tightened on the high side (1.4 V → 1.18 V).** The previous high limit (1.40 V) accepted readings 22% above the worst-case corner (1.166 V raw) — a placeholder, not a derived limit. New high limit catches any actual rail overshoot (>12.6 V would be visible). Low limit (1.00 V) is unchanged; corner is 1.007 V so a healthy unit still passes with 7 mV margin.
- **GND window tightened from 200 mV to 100 mV.** Physical worst case is ~83 mV (1.5 A through 50 mΩ + MPIO offset). 100 mV leaves a small margin. If a future fixture has worse GND cabling (>50 mΩ), the test could nuisance-fail — mitigated by ensuring the test adapter and ribbon harness meet the PCB-impedance assumption.
- **Limits derived from worst-case (not RSS) are conservative.** Some sites prefer RSS (root-sum-square) limits assuming components are independent and Gaussian; that would give windows ~15% tighter. Worst-case was chosen because (a) component count is small (3 contributors: V_rail, R_top, R_bot), (b) the test runs against a population of physical units where component skew can be systematic per-fixture (e.g. one PCB lot may have all R's biased one way), and (c) production yield benefits more from preventing nuisance fails than from catching marginal DUTs that would pass on a different fixture.
- **No per-fixture calibration.** Limits derive from datasheet worst-case. If per-fixture characterisation of the actual V_5V / V_12V rails and divider mid-points is added later, limits can be tightened per fixture.
- **GND limits assume realistic test-time current draw.** The 75 mV bound uses PWR-25's 1.5 A PTC limit; actual current at the moment the GND pins are read is typically <0.5 A (most loads off), so the 100 mV window has comfortable real-world headroom.
## Follow-up actions
1. ~~Update YAML limits~~ — done (`fe_Jx_pwr.yaml` v1.0.0).
2. ~~Document derivation~~ — done (this decision).
3. **TODO:** Capture the Test Adapter BOM into PLEASE via `please_component_create` so the 1% resistor tolerance assumption is structured, not just a comment in the YAML.
4. **TODO:** After ≥10 production runs, pull SPC stats and verify Cpk ≥ 1.33 on all 28 measurements. If margins are excessive, consider tightening (especially GND).
5. **TODO:** Cross-reference D.04 from PLEASE test cases PT-PWR.01..02 (if/when those exist) once a coverage matrix is built for fe_Jx_pwr's pt_codes. |
|
| 2026-05-25 14:29:21 |
martin.johansson@esharp.se |
update |
requirement #67 |
mcp |
show diff
| Field | Before | After |
|---|
| acceptance | Pin inventory per Sparrow Hardware Datasheet v3 §4 (sourceRef: ESH10000633/R1/02_Implementation/Sparrow Hardware Datasheet-v3-20260504_150735.pdf): J4 — 8 differential AIN channels (AIN_P/N_CH1..8, 16 pins), 5V/12V/GND; J5 — MPIO_0..3 (4), FIXED_LOAD_0..3 (4), TACHO_0..1 (2), PWM_0..1 (2), LATCH_0..1 (2), VREF (1 net, 2 pins), 5V/12V/GND; J6 — MIC_IN_L/~/R/~ (4 pins), LINE_OUT_L/~/R/~ (4 pins), AUDIO_GND (8 pins one net), 5V/12V/GND; J7 — FE_MPIO_0..11 (12), RELAY_1..4 (4), 5V/12V/GND; J8 — VLOAD_POS_0/1, VLOAD_NEG_0/1, VREM_0/1, VPSU_0/1, VSENSE+_0/1, VSENSE-_0/1, 5V/12V/GND; J9 — SCL_SLV, SCL_MSTR, SDA_SLV, SDA_MSTR, EXT_VIO, RS485_RX±, RS485_TX±, 1V8_EXT, 3V3_EXT, 12V_EXT, VADJ, 5V/12V/GND; Audio DSUB-9 — LINE_OUT_L/~/R/~, MIC_IN_L/~/R/~, AUDIO_GND (mirrors J6 nets); Active Load Phoenix — VLOAD_POS_0/1, VREM_0/1, VLOAD_NEG_0/1; PSU Phoenix (optional) — VPSU_0/1, VSENSE+_0/1, VSENSE-_0/1, GND; PoE — PWR, GND. Each functional group above must map to ≥1 PT-* test case; the fixture-electronics-test orchestrator must invoke a sub-test that exercises each group; gaps tracked via please_coverage_gap. | Pin inventory per Sparrow Hardware Datasheet v3 §4 (sourceRef: ESH10000633/R1/01_ProductSpec/Sparrow Hardware Datasheet-v3-20260504_150735.pdf): J4 — 8 differential AIN channels (AIN_P/N_CH1..8, 16 pins), 5V/12V/GND; J5 — MPIO_0..3 (4), FIXED_LOAD_0..3 (4), TACHO_0..1 (2), PWM_0..1 (2), LATCH_0..1 (2), VREF (1 net, 2 pins), 5V/12V/GND; J6 — MIC_IN_L/~/R/~ (4 pins), LINE_OUT_L/~/R/~ (4 pins), AUDIO_GND (8 pins one net), 5V/12V/GND; J7 — FE_MPIO_0..11 (12), RELAY_1..4 (4), 5V/12V/GND; J8 — VLOAD_POS_0/1, VLOAD_NEG_0/1, VREM_0/1, VPSU_0/1, VSENSE+_0/1, VSENSE-_0/1, 5V/12V/GND; J9 — SCL_SLV, SCL_MSTR, SDA_SLV, SDA_MSTR, EXT_VIO, RS485_RX±, RS485_TX±, 1V8_EXT, 3V3_EXT, 12V_EXT, VADJ, 5V/12V/GND; Audio DSUB-9 — LINE_OUT_L/~/R/~, MIC_IN_L/~/R/~, AUDIO_GND (mirrors J6 nets); Active Load Phoenix — VLOAD_POS_0/1, VREM_0/1, VLOAD_NEG_0/1; PSU Phoenix (optional) — VPSU_0/1, VSENSE+_0/1, VSENSE-_0/1, GND; PoE — PWR, GND. Each functional group above must map to ≥1 PT-* test case; the fixture-electronics-test orchestrator must invoke a sub-test that exercises each group; gaps tracked via please_coverage_gap. |
|