Mini-PSU
ESH10000662 · Rev R1
2-channel programmable buck-boost PSU Comtop Module. LT3942-based converters, 20V input, 0–24V/1.5A per channel output, DAC-controlled (VSET/ISET via AD5593R). VMON1/VMON2 output monitoring, PWM1n/PWM2n GPIO outputs via PI4IOE5V6416 expander. R1 adds VMON monitoring (ECO-012/013) and PWM expander relocation (ECO-010/011).
Project visibility
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Everything here lives inside a Project (a code + revision, e.g. ESH10000540 R3).
The backbone is the V-model, read top-to-bottom: define what the product must do, plan how to prove it,
execute the proof on real units, then learn from the field — and the Loop closes back up to the top.
This map is live: a block is green with a count when this project actually has that entity,
and dashed/dim when it’s empty. Click any block to open its tab; hover for details.
Arrows are the meaningful links; the implicit “belongs to this Project” edge is left out for legibility.
What each thing means
- Requirement
- One thing the product must do or satisfy — the “what”.
- Test Case
- A defined check that proves one or more requirements — the “how we prove it”. A verified_by trace link ties a test case to the requirement(s) it covers; that link is exactly what Coverage % counts. (So: a test case refers to the requirements it verifies.)
- Verification Plan
- A named grouping of test cases, approved before a test campaign and optionally gated by a milestone.
- Verification Record
- The result of running one test case against one unit: pass / fail / error / na. This is the evidence a requirement is actually met.
- DUT
- Device Under Test — an individual physical unit (by serial number) that records and test data attach to.
- Deviation
- A documented waiver against a verification record (e.g. accept a known non-conformance, with justification).
- Entry
- A knowledge note: a decision (settled choice), notice (assumption / risk / open question), issue (tracked problem), or concept (idea under exploration). It can attach to any other entity.
- Design Rule
- A reusable, checkable engineering constraint. Running the checks turns each violation into a Conflict.
- Conflict
- An open flag raised by a failed design-rule check (or an end-of-life / component-library issue) that needs resolving.
- Milestone
- A dated gate; verification plans can be tied to it.
- Interface / Port
- A contract between projects; each port can be driven by a requirement (and cascade one into the connected project).
- GRR Study
- A Gauge R&R study measuring how repeatable a test case’s measurement is.
- Test Data
- Production / Assert run results recorded against DUTs — the population behind a single verification record.
Plan & time
Allocation grid →Nobody is allocated to this project in the next 8 weeks.
Nothing written for this week yet.
Nobody has written a narrative for this project yet.Timeline
Color = derived gate state · hover a tile for its note.Status & gates
Chronological — Release is the final gate. Derived & read-only; edit viatrace_milestone_* tools.Release / Readiness overdue / blocked 3/6 met1 failing
pending Requirements approved
- REQ-007: draft
- REQ-008: draft
met Coverage ≥ 100%
- 6/6 requirements covered (100%)
failing All test cases pass
- 20/25 passed
- 5 failing: TC-F-04, TC-P-04, TC-M-03, TC-B-04, TC-T-00
pending No blocking issues open
- E-009: open blocker
Test Cases
Coverage — 100.0% · Done — 50.0%
| Code | Kind | Title | Severity | Scope | Status | Milestone | Created |
|---|---|---|---|---|---|---|---|
E-008 |
notice | R24/R58 38.3kΩ applied to DUT-01 — BOM and ECO-015 not yet updated | info | action | open | — | 2026-05-27 |
E-009 |
notice | BLOCKING: REQ-002 (1.5A/ch @ 24V) not demonstrated — R17/R49 rework pending | blocking | action | open | — | 2026-05-27 |
E-010 |
decision | Rename OUT1n/OUT2n → OUT1_N/OUT2_N | warning | action | open | — | 2026-05-27 |