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Mini-PSU Precision Module

ESH10000690 · Rev R0

in_progresselectronics

Mini-PSU Precision Module — R0. 2-channel adjustable light-table power (0–24 V / up to 1.5 A) with precision current/voltage control. Sub-assembly of the Collimator LED Control Box (ESH10000672 R1).

Lineage: based on ESH10000662 (Mini-PSU) — completely shared PCB. ESH10000662 is tuned for power; ESH10000690 is tuned for current precision. The functional difference is set mostly by resistor values (current-sense shunts / control scaling), not by layout. ESH10000662 is intentionally not part of the ESH10000672 R1 stack — the customer wants the slimmer precision variant. (See related_to link.)

Lightweight shell — full new_project workflow pending. Imported as a dependency of ESH10000672 R1.

Reports Milestones (2)Audit Log

Everything here lives inside a Project (a code + revision, e.g. ESH10000540 R3). The backbone is the V-model, read top-to-bottom: define what the product must do, plan how to prove it, execute the proof on real units, then learn from the field — and the Loop closes back up to the top.
This map is live: a block is green with a count when this project actually has that entity, and dashed/dim when it’s empty. Click any block to open its tab; hover for details. Arrows are the meaningful links; the implicit “belongs to this Project” edge is left out for legibility.

What each thing means

Requirement
One thing the product must do or satisfy — the “what”.
Test Case
A defined check that proves one or more requirements — the “how we prove it”. A verified_by trace link ties a test case to the requirement(s) it covers; that link is exactly what Coverage % counts. (So: a test case refers to the requirements it verifies.)
Verification Plan
A named grouping of test cases, approved before a test campaign and optionally gated by a milestone.
Verification Record
The result of running one test case against one unit: pass / fail / error / na. This is the evidence a requirement is actually met.
DUT
Device Under Test — an individual physical unit (by serial number) that records and test data attach to.
Deviation
A documented waiver against a verification record (e.g. accept a known non-conformance, with justification).
Entry
A knowledge note: a decision (settled choice), notice (assumption / risk / open question), issue (tracked problem), or concept (idea under exploration). It can attach to any other entity.
Design Rule
A reusable, checkable engineering constraint. Running the checks turns each violation into a Conflict.
Conflict
An open flag raised by a failed design-rule check (or an end-of-life / component-library issue) that needs resolving.
Milestone
A dated gate; verification plans can be tied to it.
Field Issue (RMA)
A failure reported from the field on a returned unit; Root-Cause Analysis explains why it happened.
The Loop (S-16)
loop_trace reconciles a field issue against that unit’s own verification record (did it pass at the edge of the band?). closes_loop records the corrective decision or design rule so the lesson is captured — and clears the project’s open-loop count.
Interface / Port
A contract between projects; each port can be driven by a requirement (and cascade one into the connected project).
BOM Component
A part on this project’s bill of materials, optionally linked to the shared Component Library.
GRR Study
A Gauge R&R study measuring how repeatable a test case’s measurement is.
Test Data
Production / Maestro run results recorded against DUTs — the population behind a single verification record.
0% Coverage
0% Done
0 Requirements
9 Test Cases
3 Open Entries

Timeline

Color = derived gate state · hover a tile for its note.
marker
Tape-out (PCB to JLC)
Jul 3, 2026
marker
Bring-up
Jul 17, 2026
not started
🏁 Release
· 3/6

Status & gates

Chronological — Release is the final gate. Derived & read-only; edit via trace_milestone_* tools.
MS-001Tape-out (PCB to JLC) markerdue 2026-07-03
MS-002Bring-up markerdue 2026-07-17
Release / Readiness not started 3/6 met
pending Requirements approved
  • REQ-005: draft
  • REQ-001: draft
  • REQ-007: draft
  • REQ-009: draft
  • REQ-006: draft
  • REQ-002: draft
  • REQ-003: draft
  • REQ-004: draft
  • REQ-008: draft
  • REQ-010: draft
pending Coverage ≥ 100%
  • No requirements in scope
pending All test cases pass
  • 0/9 passed
  • 9 not yet run
met No blocking issues open
met Deviations resolved
met Interfaces frozen
Blocked 9 error conflicts

Test Cases

0 Pass 0 Fail / Deviated 0 N/A 9 Open0 / 9 Maestro impl.

Coverage — 0.0% · Done — 0.0%

0 Done 0 Partial 0 Not Started 0 Missing10 Draft0 Obsolete
Requirements
10 of 10
CodeTitleCategoryCoverageStatus
REQ-001 Maximum output voltage 24V per channel Performance——
REQ-002 Maximum continuous output current 600mA per channel Performance——
REQ-003 PCB hotspot ≤ 50°C at full load Performance——
REQ-004 Output voltage drift ≤ ±0.1% over 8 hours Performance——
REQ-005 Load transient ≤ 1% overshoot, recovery ≤ 5µs Performance——
REQ-006 CC limit linearity ≤ ±0.1% FS over active ISET range, 12-bit resolution Performance——
REQ-007 Output voltage linearity ≤ ±1% of setpoint over 5–24V range Performance——
REQ-008 Conversion efficiency ≥ 80% across 5–24V output range Performance——
REQ-009 Output current readback accuracy ≤ ±0.1mA Performance——
REQ-010 Passive RC filter on current-measurement ADC input Design——